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Esophageal cancer is less predictive than other diseases, and patients are usually diagnosed at an advanced stage, so effective treatment is usually too late. Therefore, this experiment proves that AI detects esophageal cancer. The diagnostic ability of the number of phases is expected to assist doctors in using endoscopy plus artificial intelligence to increase the accuracy of diagnosis of esophageal cancer. This study provided 936 images of esophageal cancer endoscopy as a training image, including 498 white light endoscopes (WLI) and 438 narrow-band imaging endoscopes (NBI) images. According to the esophageal cancerization process, it is divided into four types: metaplasia (Dysplasia), metaplasia and esophageal cancer (Dysplasia-ECA), and esophageal cancer (ECA). A Single Shot Multibox Detector (SSD) was constructed by Convolutional Neural Network (CNN), and 264 test images were prepared to evaluate the accuracy of the model diagnosis. We developed a system called DNN-CAD to identify neoplastic or hyperplastic colorectal polyps less than 5 mm. The system classified polyps with a PPV of 89.6%, and a NPV of 91.5%, and in a shorter time than endoscopists. This deep-learning model has potential for not only endoscopic image recognition but for other forms of medical image analysis, including sonography, computed tomography, and magnetic resonance images. The construction of an SSD system for detecting esophageal cancer can analyze stored endoscopic images with high sensitivity in a short time, but more training can improve the accuracy of diagnosis. The system can facilitate early detection in practice and thus have a better diagnosis in the future.

The dynamic prompt splash behavior of water drop impinging upon a natural wood surface ( Shorea spp.) was studied in this work. The water drop images during the impacting process were taken sequentially to study the properties of the emitted droplets such as the critical Weber number, droplet number, shape, velocity, size, and kinetic energy. For prompt splashing on a Shorea spp. surface, the emitted droplets formed not only during their advancing wetting process but also during the drop receding process. The emitted droplets that formed at the early stage usually had greater velocity but significant deformation. The kinetic energy of the emitted droplets varied with great scattering at every impact height, but the average kinetic energy (KE avg ) of the droplets varied linearly with the impact height: KE avg (erg) = 0.0017 (m 0 gH), implying that every emitted droplet had approximately 0.17% of the initial potential energy of the impacting water drop. Furthermore, the number of emitted droplets depended linearly on the Weber number: N = 0.304 ( We –77).

With the rapid development of information technology and social networking, collaborative efforts are usually required to build the consensus for some transdisciplinary projects. Therefore, the collaborative ability becomes an indispensable ability to maintain competitiveness for individuals. This study proposes a CBR-based approach to enhance the students’ collaborative design abilities by utilizing domain knowledge and previous user experience. The experiment has been done in new media capstone project to evaluate the performance of this approach.

This article presents a design approach of a band-pass filter which is fabricated on an integrated passive device process and is capable of operating over the unlicensed 60-GHz band (57–64 GHz). The band-pass filter proposed in this article evolves from a typical one comprising two identical, mirrored open-loop half-wavelength microstrip line resonators. The experimental results demonstrate an insertion loss of less than 2.4 dB, a return loss of better than 10 dB over the 60-GHz band, and a 3-dB bandwidth of 24 GHz (∼42%). The simulation and measurement results are well matched up to 110 GHz. This filter is suited for system-in-a-package V-band front-end systems. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:199–202, 2016

In this paper, we propose an innovative board game design process to help students to design a cybersecurity board game with a pre-designed board game tool kit, and help them to further learn cybersecurity knowledge by using the design thinking and learning-by-doing strategies. In the process, the board game design course will firstly be given, the CBR-based learning by doing scheme will then be provided for helping the students to develop a similar game by themselves, and finally a preliminary assessment including the questionnaire and the concept map testing will be conducted. The experimental results showed that the given appropriate learning scaffolding can guide students to stimulate the creativity and complete their own cybersecurity board game in a short period of time. Besides, the questionnaire survey result also showed that about 80% of students are very interested in the board game design course, and that they can be able to understand the most frequent attacking techniques.

In microelectronic packaging industry, solder joints are used to form an electrical and mechanical connection, which can be viewed as a kind of "Electrical Glue" between package elements. The integrity of solder joints plays an important role in the reliability of the end-use electronic products. Any interface micro-voids existed in two neighbored layers will undoubtedly degrade the robustness of a solder joint and raise serious reliability concerns. The formation of these Cu/Cu micro-voids at interface will weaken the bonded interface, and easily leading to brittle interfacial fracture when the solder interconnects is subjected to an unexpected shear or pull stress, thus, the study of micro-voids formation and the approach to resolve it become more and more significant. Thus, the objective of this study will focus and emphasize on exploring one of the suspected factors to cause Cu/Cu interface micro-voids formation: "Photoresist", and the way to lower even eliminate the unwelcome Cu/Cu micro-voids defect. Since both positive and negative acting type photoresist have their own advantages as well as applications in current technology, we will use negative photoresist as control group and take positive photoresist as test condition to explore the role of "Photoresist" on the formation of Cu/Cu micro-voids under same experimental conditions in the present study. Experiment results and the promising improvement actions for reducing Cu/Cu micro-voids will be discussed and studied step-by-step in detail as well in this paper.

In 2017 ECTC, we demonstrated an on-chip thick copper "Air-core" inductor integrated with proposed WLCSP-like packaging solution. This year, the spotlight of the upgraded on-chip inductor package is two-fold. The first is a planar magnetic (MAG) film with high permeability is integrated into the inductor. The second is the thickness of the Cu redistribution layer (RDL) becomes 3~4 fold thicker than that used in typical WLCSP. These two paths are used for achieving superior inductance as well as electrical performance. The integrity of "Metal Contact Via" plays an important role on the realization of the on-chip MAG thick Cu inductor package. Two key process issues relating to metal contact at via area will be disclosed and focused for the first time. Two novel concepts ("Patterned Metal-Cut Protection Layer (PMCPL)" & "Multilayer-Etching Stop Layer (M-ESL))" are introduced for the via process improvement. The issues, the fundamental root cause, and the improvement actions will be discussed step-by-step in this paper. In short, without such two imperative improvement approaches as just mentioned, not only will the device function open (fail), but the excellent electrical performance will not be realized as well. At last, compared to the air-core thick copper inductor package reported last year, the results show that the inductance density can boost up 9-fold and the direct resistance (Rdc) significantly reduces 2-fold.

With the rapid growth of the Internet-based smart mobile phone applications, a variety of sophisticated threats or attacks have been developed on the Internet recently. Therefore, how to enhance the cyber-security literacy education to prevent or mitigate Internet crimes becomes a very important and challenging issue. In this paper, the frame structure of the knowledge base for the card game called iMonsters has been designed to help students to easily understand the attack or defense strategies and concepts in cyber-security domain, and the ontology crystallization method will be applied to refine the existing ontology. We then propose a rule generation algorithm to generate new rules based upon learning from examples approach, and the generated new rules can be used as the scaffoldings to help the users to learn the knowledge obtained from the real cases. 53 children have participated in the iMonster card game playing in 2015. Based upon the experimental results, we can find that the card game playing can assist students to learn the cyber-security knowledge.

AlGaN/GaN dual metal Schottky barrier diodes (SBD) are demonstrated on a silicon substrate. The anode is composed of two metals with different work functions to achieve a better trade-off between the forward and the reverse characteristics. The low work function metal Ti reduces the turn-on voltage and the high work function metal Ni at the edge of the anode reduces the reverse leakage current and maintains the breakdown voltage. The turn-on voltage of the Ni-SBD is reduced from 1.47 V to 0.57 V by employing the dual metal anode, and the breakdown voltages are virtually unaffected.

Implementation of thick Cu inductor in IC chips has been a highly challenging task for Far-backend packaging industry. One of the major concerns is that the thicker Cu trace wrapped by re-passivation polymer layers (Polymer-1 & Polymer-2) is often accompanied by remarkable internal stress in the overall package, which is plagued with the risk of layer-to-layer delamination and/or interface micro-cracks. In this paper, a thick Cu inductor integrated with a WLCSP-like packaging solution is demonstrated for the first time through delamination improvement, which depends strongly on both (1) via-opening (etching) and (2) post top copper treatment processes in the specific scheme. In the via-opening (etching) process, an optimized etching method is proposed to minimize the surface roughness (Ra) of polymer-1 to 2~3 nm and concurrently achieve byproducts free. On the other hand, for the subsequent post top copper treatment processes, the introduced XYZ plasma and wet clean treatment are carried out to enhance the seed layer removal efficiency. As a result, the metal residue is substantially reduced to lower than 0.1% from 1.7% according to XPS analysis. The XYZ plasma treatment also benefits the surface roughness (Ra) of polymer-1 to around 30~35 nm, which is sufficient for later polymer-1 & -2 interface adhesion. These treatment approaches will be systematically presented and discussed in detail with experimental evidence. By means of the surface modification approaches reported in this study, the interface delamination phenomenon was greatly improved. The thicker Cu on-chip inductor embedded with WLCSP-like package successfully passed multi-reflow with 10 cycles and component level reliability tests, such as MSL1+HTS500hrs and MSL1+u-HAST96hrs. Meanwhile, compared to common planar spiral inductors fabricated by Fab process, not only was the inductance boosted, but the Cu trace resistance is also greatly reduced 10-fold. Moreover, the most striking feature of this packaging solution is that one can insert some novel high-permeability materials into this novel packaging scheme for much better electrical performance simply depending on customer requirements and designs.

Ruthroff-type transmission line transformers (TLTs) and baluns prevail over their broadband and low-loss performance. A typical Ruthroff-type balun with a 1:4 step-up impedance transformation ratio was successfully presented using integrated passive devices (IPDs) process. Moreover, two proposed baluns with step-down impedance transformation ratios of 1:1 and 9:4 were developed by modifying the combination of one Ruthroff-type TLT and one Ruthroff-type balun. The two proposed impedance step-down baluns whose balanced impedance is lower than unbalanced impedance make Ruthroff-type balun more flexible for applications; meanwhile, fabricating the baluns using IPD process can help to enhance the low-loss performance. The measured results show that the proposed 1:1 balun exhibits an insertion loss of 0.46 dB with 1-dB fractional bandwidth of 138.9%, and the proposed 9:4 balun exhibits an insertion loss of 0.75 dB with 1-dB fractional bandwidth of 72.4%. The chip areas of the proposed 1:1 and 9:4 baluns, including the pads, are 0.6 and 0.64 ${\rm mm}^{2}$ , respectively. The two proposed baluns are the first on-chip step-down Ruthroff-type baluns and having an option of center tap, which is highly contributive to wideband and high-efficiency power amplifier design.

Strontium zirconate nickelate [(SZN); Sr0.69Ni0.47Zr0.085O3.75] was synthesized through a sol-gel method by adding nickel (II) acetylacetone instead of titanium isopropoxide, which can effectively make thin films smoother and further act as gate insulators applied in pentacene-based thin-film transistors. Sol-gel SZN thin films were investigated by X-ray photoelectron spectroscopy and atomic force microscopy to confirm the chemical composition and smooth surface roughness, and the latter property was found to be compatible for pentacene thin film growth. Thus, the electrical characteristics of pentacene-based transistors exhibited a high mobility of 10.04 cm2 V-1s-1 low threshold voltage of -1.51 V,, and low subthreshold swing slope of 350 mV/decade. To realize high mobility mechanisms, intermolecular coupling and reorganization energy of pentacene thin films were introduced. Another purpose of this introduction was to evaluate the higher hopping rate of carriers between the adjacent pentacene molecules on SZN derived from the March-Hush equation than other high-κ traditional sol-gel insulators.

A high-gain gate-pumped down-conversion mixer at 60 GHz is realized in a standard 90-nm CMOS process. The proposed mixer adopted a Darlington cell and a microstrip-line Lange coupler to yield wide 3-dB bandwidth from 5 to 65 GHz. The measured performance demonstrates a conversion gain (CG) of 6 dB at 4.2-mW power consumption. The maximum CG is 6.5 dB at 36 GHz. This mixer is then integrated with a three-stage low-noise amplifier, to form a 60-GHz receiver front-end. The receiver achieves a CG of 28 dB with a noise figure of 7.1 dB at 20-mW power consumption from a 1-V supply voltage. The 3-dB RF bandwidth is 14 GHz.

Cathode buffer layers (CBLs) can effectively further the efficiency of polymer solar cells (PSCs), after optimization of the active layer. Hidden between the active layer and cathode of the inverted PSC device configuration is the critical yet often unattended vertical diffusion of the active layer components across CBL. Here, a novel methodology of contrast variation with neutron and anomalous X-ray reflectivity to map the multicomponent depth compositions of inverted PSCs, covering from the active layer surface down to the bottom of the ZnO-based CBL, is developed. Uniquely revealed for a high-performance model PSC are the often overlooked porosity distributions of the ZnO-based CBL and the differential diffusions of the polymer PTB7-Th and fullerene derivative PC71 BM of the active layer into the CBL. Interface modification of the ZnO-based CBL with fullerene derivative PCBEOH for size-selective nanochannels can selectively improve the diffusion of PC71 BM more than that of the polymer. The deeper penetration of PC71 BM establishes a gradient distribution of fullerene derivatives over the ZnO/PCBE-OH CBL, resulting in markedly improved electron mobility and device efficiency of the inverted PSC. The result suggests a new CBL design concept of progressive matching of the conduction bands.

Pentacene-based organic thin-film transistors with solution-processed barium zirconate titanate dielectric layers are demonstrated. According to the programming/erasing operations, the devices exhibited memory characteristics, such as reversible threshold voltage shifts and nondestructive readout. In addition, the reliability of the memory devices was confirmed by data retention time and repeated switching cycles' endurance testing. In addition, the possible mechanism of the memory effect was also discussed. These results suggest that the devices could potentially be applied to nonvolatile memory applications in organic electronics.

This study presents an asymmetric broadside coupled balun with low-loss broadband characteristics for mixer designs. The correlation between balun impedance and a 3D multilayer CMOS structure are discussed and analyzed. Two asymmetric multilayer meander coupled lines are adopted to implement the baluns. Three balanced mixers that comprise three miniature asymmetric broadside coupled Marchand baluns are implemented to demonstrate the applicability to MOS technology. Both a single and dual balun occupy an area of only 0.06 mm2. The balun achieves a measured bandwidth of over 120%, an insertion loss of better than 4.1 dB (3 dB for an ideal balun) at the center frequency, an amplitude imbalance of less than 1 dB, and a phase imbalance of less than 5deg from 10 to 60 GHz. The first demonstrated circuit is a Ku-band mixer, which is implemented with a miniaturized balun to reduce the chip area by 80%. This 17-GHz mixer yields a conversion loss of better than 6.8 dB with a chip size of 0.24 mm2. The second circuit is a 15-60-GHz broadband single-balanced mixer, which achieves a conversion loss of better than 15 dB and occupies a chip area of 0.24 mm2. A three-conductor miniaturized dual balun is then developed for use in the third mixer. This star mixer incorporates two miniature dual baluns to achieve a conversion loss of better than 15 dB from 27 to 54 GHz, and occupies a chip area of 0.34 mm2.

In this paper, we demonstrate the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) with TaN metal-gate and HfO 2 gate dielectric to achieve high performance characteristics. A high performance LTPS-TFT with low threshold voltage 0.9 V, excellent subthreshold swing 0.15 V/decade and high I on / I min current ratio 1.9 × 10 6 are derived without any hydrogen treatment. In addition, we also introduce the fluorine implantation prior to the Si thin-film crystallization to passivate the defects in grain-boundaries of the channel film and HfO 2 /polysilicon interface. Significant improvements on subthreshold swing and I min are observed. In addition, the transconductance degradation and threshold voltage instability due to hot carrier stress is also investigated, respectively. Finally, we derive a high reliability and performance LTPS-TFT with low threshold voltage ∼1.38 V, ultra-low subthreshold swing 0.132 V/decade and high I on / I min current ratio 1.21 × 10 7 , which is suitable for the application of system-on panel (SOP).

In this letter, 65-nm node silicon-on-insulator devices with high-kappa offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-kappa offset spacer dielectric can effectively increase the on-state driving current ION and reduce the off leakage current IOFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the ION/IOFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-kappa offset spacer dielectric

An active power filter with asymmetric inverter legs are presented to eliminate harmonics, compensate reactive power and draw the balanced line current from the AC source under balanced and unbalanced load conditions. Three inverter legs are used in the adopted voltage source inverter. In each leg, four active switches are adopted to achieve three-level pulse-width modulation (PWM). No clamped diode or flying capacitor is used in the proposed inverter. In the adopted control algorithm, a classical proportional-integral voltage controller and hysteresis current controller are used to maintain DC-link voltage constant and to track line current commands, respectively. A voltage compensator is added in the inner control loop to compensate the neutral point voltage variation due to load variation. Based on the proposed PWM control scheme, a three-level voltage pattern is generated on the AC terminal of the inverter. The system configuration and mathematical analysis are discussed in the paper. Finally, the experimental results based on a laboratory scaled down prototype are provided to verify the effectiveness of the control algorithm.

A variable gain low noise amplifier (VGLNA) using a 0.35 μm SiGe HBT process is described. A VGLNA with linear gain control and high linearity has been developed for 2.4 GHz ISM band applications. The gain control circuit is achieved without degrading either the input or the output VSWR. This technique can also simultaneously realize low noise figure and high linearity. The designed VGLNA achieved a gain of 19 dB, a noise figure of 2.7 dB, a third-order intercept point of −12 dBm, and a linear gain control range of 7.2 dB. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 42–45, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22052

A three-phase four-wire power factor corrector based on neutral-point-clamped (NPC) topology is adopted to reduce the current harmonics and increase the input power factor. Using the NPC topology, the voltage stress of power switches can be reduced to the half of the dc-link voltage. With the dc-link voltage controller and the phase locked loop circuit, the balanced and sinusoidal line currents can be drawn from the ac supply system under the balance and unbalance mains voltages. The hysteresis current comparators are adopted in the current control loop to track the line current commands. Three voltage levels are generated on the ac terminal to the neutral point. Simulations and experiments are provided to verify the validity and the effectiveness of the proposed control scheme.

This study provides new evidence on a long postulated mechanism of phase separation in a polymer/fullerene mixture during spin coating for controlled nanodomains of oriented crystallization and heterojunctions that favor applications in polymer solar cells (PSCs). The simultaneous nanoscale phase separation and crystallization during spin coating of the mixture are traced using in situ grazing-incidence small- and wide-angle X-ray scattering. Combined with the complimentary results from time-resolved optical reflectance spectroscopy, transient stratification of the liquid film during the transition from the flow- to evaporation-dominated stage of spin coating is disclosed; the vertical liquid–liquid phase separation incubates a supersaturated skin layer where fullerene aggregation and polymer crystallization occur and develop concomitantly. Shortly after the transition, the near-surface structural development is largely pinned, leaving the solvent-rich bottom layer to diminish via solvent diffusion and evaporation through the thickened skin layer that finally condenses into the spin-coated film upon solvent depletion. The shear-enhanced surface layering and supersaturation for the surface-down nanostructural development are unexpected in all the existing structural models for PSCs. The mechanistic understanding of coupled vertical phase separation and local nanosegregation provides new insights and alternative strategy to the morphology control of spin-cast PSC active layers in particular and various solution-processed polymeric films in general.

A 25-75 GHz compact double balanced frequency doubler fabricated in standard 0.18-mum CMOS process is demonstrated. The resistive doubler is composed of two identical asymmetric broadside-coupled baluns, and a quad GS-connected diode. The fabricated doubler achieves a radio frequency bandwidth from 25 to 75 GHz with a maximum output power better than +3 dBm; the fundamental signal rejection is ranging from 32 to 59 dB, and only occupies a chip size of 0.24 mm2. To the knowledge of the authors, this double balanced frequency doubler is the first demonstration with an operating frequency up to 75 GHz in 0.18-mum CMOS technology and shows this silicon-based frequency doubler can compare with its GaAs counterpart.

In this letter, fluorine ion implantation with low- temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO2 low-temperature poly-Si thin- film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of Imin is achieved because 25% grain- boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO2 gate dielectric and fluorine preimplantation can simultaneously achieve low VTH ~ 1.32 V, excellent subthreshold swing ~0.141 V/dec, and high ION/Imin current ratio ~1.98 times 107.

A compact V-band star monolithic microwave integrated circuit mixer has been designed using compensated overlay capacitors in dual baluns for the input of local oscillator and radio frequency ports. The reduced-size balun can be simply realized by shunting overlay capacitor in either input or end of balun. The proposed V-band star mixer achieved a conversion loss of 8.6 dB, the port-to-port isolations better than 18 dB, and an input 1-dB compression point higher than 7.7 dBm at 60 GHz. Moreover, better than 50% length reduction of dual balun was achieved, and chip size of star mixer including pads was less than 0.68 times 0.59 mm2.

A 16-46 GHz mixer using broadband balun fabricated in standard 0.18-mum CMOS process is demonstrated. The broadside-coupled balun with wide bandwidth and low insertion loss utilizes the inherent 3D multilayer structure in CMOS process. The mixer exhibits radio frequency bandwidth from 16 to 46 GHz with a conversion loss ranging from 13 plusmn 1.5 dB, and achieves bandwidth over 103% with a compact chip size of 0.24 mm2.

This work presents a miniature Q-band balanced single side-band sub-harmonically pumped image rejection diode mixer (SHIRM) using a compact Marchand dual balun design. The SHIRM is realized employing four anti-parallel diode pairs for frequency mixing, a Lange coupler for radio frequency (RF) signal input, and a reduced size three-conductor-line Marchand dual balun for local oscillator pumping. The length of three-conductor-line dual balun is reduced by 81% after shunting two lumped capacitors at the center conductor. The measured results exhibit a minimum conversion loss of 8.6 dB, a maximum image rejection ratio of 22 dB, all ports isolation better than 37 dB, and an input 1-dB compression point of 2.5 dBm at RF bandwidth of 40.5 to 43.5 GHz and fixed intermediate frequency of 2.4 GHz. The chip area is very compact, only 1 times 0.84mm2