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In this study, we propose technologies for the device structure, gate fabrication process, and back-bias-assisted operation of Si spin qubits to realize the high robustness of the two-qubit SWAP gate operation against process variations. We performed quantum device simulations for MOS-type two-qubit devices and verified the benefits of these technologies on the SWAP gate fidelity. We clarified that these technologies significantly improve the robustness of the SWAP gate operation against process variations and achieve a 6σ-yield SWAP gate operation with 99% fidelity, assuming device size fluctuation of the International Roadmap for Devices and Systems (IRDS) target for 2022. The proposed technologies provide a solution for completing a universal quantum gate set for realizing universal quantum computers with silicon.

We simulate the static behavior of Ge-p/Si-n nanosheet complementary FETs (CFETs), where p-type FETs containing Ge nanosheet channels are stacked on top of n-type FETs containing Si nanosheet channels, and we investigate its relation to temperature while comparing it with that of Si-p/Si-n nanosheet CFETs, whose p-type FETs contain Si nanosheet channels. It is found that temperature rise has similar effects on the static characteristics of the two CFETs operating as inverters, although the variations in threshold voltage and noise margin with rising temperature are slightly smaller in the Ge-p/Si-n CFET inverter than in the Si-p/Si-n CFET inverter. The temperature rise effects are fully explained by the temperature dependence of material and carrier properties of Ge and Si.

A new device simulator named Impulse TCAD was developed, being built on top of a nonlinear finite volume method solver, which is further based on the Python script language and its associated scientific libraries. The user can fully customize the device properties and/or equations using scripts, which allows ready handling of exotic materials with nonstandard physical models. As a demonstration, a transient analysis of a negative-capacitance field-effect transistor (NC FET) is presented. The ferroelectric material in the NC FET is handled by using the time-dependent Ginzburg–Landau–Devonshire (GLD) equation, while standard device equations are applied for the rest of the device. The simulations show that, starting from the spontaneous polarization state, the ferroelectric regions evolve into the negative-capacitance regime, showing the expected characteristics of a NC FET. They also indicate that the Ginzburg term in the GLD equation, which is related to the correlation radius $$r_{\mathrm{c}}$$ , plays an important role in the appearance of the negative-capacitance effect. When $$r_{\mathrm{c}}$$ is too short compared with the channel length, the ferroelectric region becomes segregated into multiple polarization domains, resulting in loss of the NC FET characteristic.

We propose a buried nanomagnet (BNM) realizing high-speed/low-variability silicon spin qubit operation, inspired by buried wiring technology, for the first time. High-speed quantum-gate operation results from large slanting magnetic-field generated by the BNM disposed quite close to a spin qubit, and low-variation of fidelity thanks to the self-aligned fabrication process. Employing TCAD-based simulation, we demonstrate that the BNM realizes 10 times faster Rabi oscillation (faster spin-flip) than previous works and >99% fidelity under certain process variations. Also, the proposed BNM arrangement is implementable for error-correctable large-scale quantum computers employing a 2D-latticed qubit layout. This technology paves the way to practical large-scale quantum computers with silicon.

We developed an integrated device simulator for quantum bits (qubits) based on an in-house technology computer-aided design (TCAD) simulator. The simulator outputs quantum transport and qubit operations simultaneously. We present several technologies that were developed and implemented on a device simulator for the first time: a quantum and semi-classical hybrid calculation scheme for the potential, fictitious charge method for the capacitance, modified Ampere's equations for the magnetic field, and multi-channel analysis for quantum transport.

We perform TCAD simulation for TMDC channel TFETs with the material parameters considering ab initio band structure. By using the WKB-based nonlocal band-to-band tunneling (BTBT) model with the above parameters, we find that the current voltage characteristics of the TFETs are in good agreement with those obtained by microscopic NEGF calculation. Based on this approach, we also investigate the dependence of tunnel leakage current on the gate length. Our simulation method paves the way for reliable macroscopic device simulations for TMDC channel TFET.

A Python-based device simulator named Impulse TCAD was developed. The simulator is built on top of a nonlinear finite volume method (FVM) solver. To describe physical behavior of non-standard materials, both device properties and their dominant equations can be customized. The given FVM equations are solved by the Newton method, where required derivatives of the equations are derived automatically by using an automatic differentiation technique. As a demonstration, a steady state analysis of the negative capacitance field effect transistors with ferroelectric materials is selected, where the coupled Poisson and Devonshire equations are implemented in several different ways.

The size and complexity of CNN models are increasing and as a result they are requiring more computational and memory resources to be used effectively. Use of a lower bit width numerical representation such as binary, ternary or several bit width has been studied extensively so as to reduce the required resources. However, the representation capability of such extremely low bit width is not always sufficient and the accuracy obtained for some CNN models and data is low. There are some prior studies that use moderate lower bit width with well-known numerical representations such as fixed point or logarithmic representation. It is not apparent, however, whether those representations are optimal for maintaining high accuracy. In this paper, we investigated the numerical quantization from the ground up, and introduced a novel "Variable Bin-size Quantization (VBQ)" representation in which quantization bin boundaries are optimized to obtain maximum accuracy for each CNN model. A genetic algorithm was employed to optimize the bin boundaries of VBQ. Additionally, since the appropriate bit width to obtain sufficient accuracy cannot be determined in advance, we attempted to use the parameters obtained by a training process using higher precision representation (FP32), and used quantization in inference only. This reduced the required large computational resource cost for training. During the process of tuning VBQ boundaries using a genetic algorithm, we discovered that the optimal distribution of bins can be approximated by an equation with two parameters. We then used simulated annealing for finding the optimal parameters of the equation for AlexNet and VGG16. As a result, AlexNet and VGG16 with our 4-bit quantization achieved top-5 accuracy at 74.8% and 86.3% respectively, which were comparable to 76.3% and 88.1% obtained by FP32. Thus, VBQ combined with the approximate equation and the simulated annealing scheme can achieve similar levels of accuracy with less resources and reduced computational cost compared to other current approaches.

We consider a method to simulate heat transport by phonons together with charge transport by electrons and holes that is applicable to standard technology computer-aided design (TCAD) simulators. Because our proposed method handles each phonon mode separately, it can connect the atomistic calculation of phonon properties of materials directly to the TCAD simulation of the thermal behavior of semiconductor devices. We implement this method in our homemade TCAD and simulate heat generation and transport in a transistor with a thin silicon-on-insulator body using the phonon properties of Si obtained from lattice dynamics calculations. The same simulation is carried out with phonon heat transport approximated by the heat equation, and the results indicate that it is difficult for the heat equation to accurately reproduce the phonon heat transport.

A multi-flux method for semiconductor device simulation is proposed. In this method, the carrier is treated as fluid, and the current continuity equation is divided into several fluid equations. By dividing the electron current into several separate electron currents, various applications of device simulation might be enabled. This paper describes an application in which the electron current is divided into several subbands in the MOS inversion layer, and multiple electron current continuity equations for each subband are solved. For the inversion layer of the two-dimensional device simulation with the drift diffusion approximation, the energy height for each subband is obtained by the Poisson–Schrodinger method, and multiple current continuity equations corresponding to each subband are solved in order to study the quantum effects more accurately.

In this paper, for the first time, we clarified the multidomain dynamics of ferroelectric polarization in the Negative Capacitance Field-Effect Transistors (NCFETs) by an in-house Technology Computer-Aided Design (TCAD) module. It enables self-consistent simulations among the time-dependent Landau-Khalatnikov equation and the other equations that govern operation of FETs. Our simulation reveals that domain-wall thickness $T_{\text{dw}}$ , which reflects a correlation strength between domains predominates coherency of the NC polarization. In a strong correlation (large $T_{\text{dw}}$ ) case, a coherent NC polarization is realized at least to a degree of $T_{\text{dw}}$ . On the other hand, in a weak correlation (small $T_{\text{dw}}$ ) case, perturbation from peripherals easily leads to incoherence of polarization, where a uniform polarization is split into multiple spontaneous polarization domains. This coherency breaking found to give rise to deteriorated voltage amplification of NC. Design methodology to maintain the NC coherency is also proposed.

We consider the method to simulate negative-capacitance field-effect transistors having a ferroelectric film as a gate insulator in the framework applicable to technology computer-aided design device simulators and propose a method with complete applicability. In the method, the behavior of the polarization in ferroelectrics is described by the Landau-Khalatnikov equation and it is solved simultaneously with the Poisson equation to obtain the distribution of the polarization and electrostatic potential. Also, the proposed method enables the device simulators to take into account a factor related to forming domain structures of the polarization.

We propose a 9-bit floating point format for training image-classifier deep convolutional neural networks. The proposed floating point format has a 5-bit exponent, a 3-bit mantissa with the hidden most significant bit (MSB), and a sign bit. The 9-bit floating point format reduces not only the transistor count of the multiplier in the multipy-accumulate (MAC) unit, but also the data traffic for the forward and backward propagations and the weight update. Both of the reductions realize a power efficient training. To maintain the validation accuracy, the accumulator is implemented with an internal longer-bit-length floating point format while the multiplier accepts the 9-bit format. We examined this format in the training of the AlexNet and the ResNet-50 with the ILSVRC 2012 data set. The trained 9-bit AlexNet and ResNet-50 exhibited the validation accuracy superior to the 16-bit floating point format training by 1.2 % and 0.5 %, respectively. The transistor count in the 9-bit MAC unit is estimated to be reduced by 84% as compared to the 32-bit counterpart.

Stability and instability of the negative capacitance (NC) states in metal (M) / ferroelectric (F) /M /insulator (I) /semiconductor (S) structures are rigorously studied using a newly developed transient TCAD simulation, in which time-dependent Landau-Khalatnikov (LK) equation can be considered. Our transient analysis reveals that NC becomes unstable due to formation of the inversion layer and gives rise to hysteresis in the NC-state, which cannot be simulated by the steady simulation. We propose a novel FinFET, in which the F-layer is located at the gate contact holes and exhibit a design guideline to avoid the instability of the NC-state using experimentally obtained ferroelectric parameters for (Hf, Zr)O 2 .

Performances of negative capacitance FinFETs (NC-FinFETs) at sub 10 nm gate length are analyzed with a newly developed technology computer-aided design (TCAD) simulation. This simulation fully couples the Landau-Khalatnikov (L-K) equation with the physical equations for FinFETs in 3-D. It reveals an excellent immunity against short-channel effects in NC-FinFETs owing to NC-enhancement by the gate-to-drain coupling, for the first time. NC-FinFETs with a gate length of 10 nm are projected to operate with more than 26 times energy-efficiency of conventional FinFETs.

We propose a numerical method using contour integral to solve polynomial eigenvalue problems (PEPs). The method finds eigenvalues contained in a certain domain which is defined by a surrounding integral path. By evaluating the contour integral numerically along the path, the method reduces the original PEP into a small generalized eigenvalue problem, which has the identical eigenvalues in the domain. When the contour integral is approximated numerically, eigenvalues on the periphery of the path are also obtained. Error analysis shows that, even though condition numbers of those exterior eigenvalues can be huge, the interior eigenvalues are calculated less erroneously. Four numerical examples are presented, which confirm the theoretical predictions.

A parallel Fock matrix construction program for FMO-MO method has been developed with the distributed shared memory model. To construct a large-sized Fock matrix during FMO-MO calculations, a distributed parallel algorithm was designed to make full use of local memory to reduce communication, and was implemented on the Global Array toolkit. A benchmark calculation for a small system indicates that the parallelization efficiency of the matrix construction portion is as high as 93% at 1,024 processors. A large FMO-MO application on the epidermal growth factor receptor (EGFR) protein (17,246 atoms and 96,234 basis functions) was also carried out at the HF/6-31G level of theory, with the frontier orbitals being extracted by a Sakurai-Sugiura eigensolver. It takes 11.3 h for the FMO calculation, 49.1 h for the Fock matrix construction, and 10 min to extract 94 eigen-components on a PC cluster system using 256 processors. © 2010 Wiley Periodicals, Inc. J Comput Chem, 2010

We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal–oxide–semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

A moving mesh method for semiconductor device simulation is developed which effectively compromises accuracies without increasing mesh number. In this method, mesh positions are shifted referring to the solution of the previous bias condition, or to the Newton corrections. The method is applied to solve PN-junctions and MOSFETs. The method provides an effective way to cover the changes of carrier distributions depending on bias conditions. The algorithm is simple and effective, and can be widely used.