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Plasma etching and ion implantation pose a problem to circuit reliability due to its damaging effect to gate oxides of MOS devices. A simulator was developed to predict oxide failure rates during and after processing and to locate strong charging current locations in the layout which allow changes to improve circuit hot-carrier reliability. The oxide reliability of a differential pair was also simulated.

In this paper we describe a simulator which can be used to study the effects on circuit behavior of two radiation phenomena: Single Event Upset (SEU) and total-dose radiation effects. Using this simulator the user can predict the error rate in large circuits due to single event upset. The error rate model described here uses a well established methodology, but for the first time a different choice is made on picking up the sensitive nodes, enabling a quick prediction even for very complex circuits. The simulator predicts circuit behavior after total-dose irradiation using as inputs: the dose rate and the total dose parameter sets that characterize the transistor response to radiation, and the circuit netlist. The total-dose simulator is based on physical models of the changes in the MOSFET caused by radiation. We quantify the degradation of each MOSFET in a circuit with two parameters and determine the change in the MOSFET characteristics from preirradiation MOSFET data. Using the 'irradiated' MOSFET parameters, we can simulate circuit behavior using an ordinary circuit simulator such as SPICE. With this simulator, one can study how resistant a circuit is to changes due to irradiation and design circuits to be functionally radiation 'hard'. The 'double-kink' in the MOSFET subthreshold region due to the parasitic effect of the edge transistors can be simulated and the user is advised when leakage current is unacceptably large. The speed degradation of a ring oscillator was simulated and the results compared with actual measured data.

Studies on a bidirectional current reduction model that directly simulates circuit-degradation due to hot carriers reveals that the model yields results that agree well with experimental data for NMOSFET parameter such as stressing time. The model simulates hot-electron damage as a bidirectional voltage controlled current supplier. The model does not require SPICE simulation stress constrains and is compatible to all SPICE device models.