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Describes the Spine99 effort between Cadence Design Systems Inc. and Synopsys Inc. aimed at linking the physical and logical design tools through a standard `spine' of common formats. Information transfer for design flows; Objectives of the effort; Achievement of a flow that ensures timing correlation from synthesis to layout. INSETS: Information you need to know about linking synthesis to layout;Problems today with synthesis to GDS;Information you need to know about linking synthesis to layout.

Presents a roundtable discussion on the significance of formal methods for system-on-a-chip design. Aspects of formal-verification technology that continue to be contested; Property checking and model checking techniques. INSETS: Formal verification terminology.;Design verification vs. implementation... by Kurt Keutzer;How to get management to buy into...;The impact of formal verification on the...

Presents information on the process of designing a system-on-chip (SOC) with hardware and software content. Details on the asynchronous transfer mode (ATM) switch designed by design engineer Jamie Pierce; Information on the Seamless coverification environment (CVE) from Mentor Graphics; Discussion on the clones of the VirtuaLogic emulator of Ikos Systems.

Highlights various approaches that can be used to design reuse. How to use design-migration tools like LACE and DREAM to migrate a design from one process technology to another; Disadvantages of LACE; LACE's features for system-on-a-chip (SOC) design; How the LACE was compared to DREAM software; Other approaches to design migration/reuse.

Provides information regarding the use of low-power chip designs in application specific integrated circuit (ASIC) system for battery powered applications. Rules in designing low-power chips; Tools that can be used to identify power problems in system-on-a-chip designs; Information regarding power management. INSET: The key to power management--Get it right, up... by Jerry Fren.

Provides information on the system-on-a-chip (SOC) design which is constructed through integration of interrelated parts to form an application specific integrated circuit (ASIC) system. Packaging of ASIC expertise by several vendors in the market; Challenge of SOC design; Various SOC designs offered by several manufacturers. INSET: Virtual components for system-on-a-chip design, by Larry Lewis.

Presents information on the testability of Internet Protocol (IP)-based system application specific integrated circuit (ASIC). Features of Chromatic Research testability strategy; Problems of IP testability; Companies that pushes for IP testability.

Focuses on the use of a methodology involving floorplan and place-and-route tools, to conquer potential design pitfalls of applications specific integrated circuit (ASIC). Use of floorplanning in correcting timing problems; Growth in the physical design and analysis task; Timing and power tools for updating physical design flow for deep submicron; Difficulty in the implementation of hierarchical design methodology.

Discusses the impact of power on applications specific integrated circuits (ASIC) design and its effects on design technology. Role of power optimization tools; Views on power problems; Companies which offer power optimization tools; Problems in getting support from ASIC vendors. INSETS: Use accurate interconnect information,..., by Martin Walker.;Reference books on low-power design..

Discusses behavioral synthesis, an application specific integrated circuit/design tool. Some behavioral synthesizers in the market; Applications of behavioral synthesizers; Learning curve for using behavioral synthesis; Features and design flow of the tool.

Discusses the progressing high-technology industry of Israel. Gilat Satellite Networks' provision of interactive and high-speed Internet access; Technology developed by QualComm's Israeli research and development team to simulate satellites in the Globalstar; Growing number of electronic design automation (EDA) companies in Israel.

Discusses the Virtual Socket Interface Alliance (VSIA) which is the best way to protect yourself and your design project. Goals of the VSIA; One of the first decisions that one faces when selecting Internet Protocol; Six categories and suggestive checklist on having made a decision; What the VSIA wants in the Revision 1.0 of its spec.

Discusses how core-based application specific integrated circuits (ASIC) design is possible with the proper tools, methodology and support. Requirements for modelling architecture for design reuse; Utilization of Sand soft core in Creative Labs; Selection of ASIC vendor; On-chip-bus issue.

Focuses on the approaches of Application Specific Integrated Circuits (ASIC) vendors to change sign-off methodologies and tools. Shift in methodology towards static sign-off methods; Evaluation of the International Business Machine's (IBM) static-timing analyzer; Prerequisite on test patterns; Reason for changing sign-off methodology; Examples of model checkers for sign-off.

Focuses on library decision choices related to building application specific integrated circuits facing customer-owned tooling and foundry customers. Risk reduction; Investment concerns; Process migration; Layout-synthesis tools; Portability path; Layout porting. INSET: Modifying cell layouts when migrating to a new process..

Focuses on application specific integrated circuit design and design tools. Timing simulations; Verification of corner cases; Behavioral modeling; Verification productivity; Static and dynamic timing; Format tools; Hardware and software concerns. INSETS: What's what in ASIC-verification tools, by John Bierbauer.;Checking out the impact of interconnect using dynamic-timing..;ASICs paving the verification path for programmables..

Discusses the paradigm shift from gate array to cell-based application specific integrated circuit (ASIC) which is reflected in both ASIC vendors' offerings and designers choice' of technology. Advantages of cell-based ASIC; Other reasons for the popularity of cell-based ASIC; Companies that shift to cell-based ASIC; Shift of embedded array to cell-based; Building system ASIC; How to used all three ASIC technologies.

Focuses on the increase in the number of engineering designers who are embracing the HDL technology. Benefits of cycle-based simulation; Offering of two-state and four-state logic states; Support for a synthesizable subsets of an HDL; Use of third-party models with cycle-based simulators.

Focuses on the use of formal-verification tools in chip design. Benefits of using formal-verification; Comparison with simulation and emulation-based methodologies; Key features. INSET: Is it model checking, property checking, or language....

Reports on the issues discussed at the ASIC Forum in Paris, France sponsored by `Computer Design' journal. Demand for core-based application specific integrated circuit (ASIC) design; Driving forces for the ASIC market; Providing users with technology portability while supporting ASIC vendors; Intellectual property (IP) ownership and distribution. INSETS: Paris forum participants.;Hardware and software worlds..

Recommends the use of field programmable gate arrays (FPGA), application specific integrated circuits (ASIC) or cores for digital signal processing (DSP) applications. Integration and cost reduction of DSP systems in low-volume applications; Hardwiring algorithms; Dedicated logic; Core-based ASIC design; Straightforward division of hardware and software.

Reports on the growing use of gate arrays, embedded arrays and cell-based application specific integrated circuits (ASIC) for design projects. Fees for stockpiling; Migration issues; Blurring of boundaries; Gate-array prototyping; Amplification of drivers. INSETS: When does a gate array beat a standard-cell design in density..;Where GaAs gate arrays fit in the deep-submicron puzzle..

Discusses coping with deep submicron in integrated circuit (IC) design. Static-timing analysis; Timing consistency; Static, dynamic timing; Cost versus time; Emulation for submicron application specific integrated circuits (ASIC); Simulating at high level; Accelerating simulation; Formal verification. INSETS: Using formal verification for.., by Christian Berthet.;Five-million-gate ASIC project signed off with static...

Describes the trends in pre-synthesis tools for analyzing and verifying system-on-a-chip designs. Verification tools developed by SureFire Verification and InterHDL; Use of solving techniques derived from simulation, synthesis and formal verification; Automation of recurring process in the design flow within an existing environment.

Reports on the 1999 Design Automation Conference. Exhibitors; Introduction of tools and methodologies that increase verification productivity; Transparent model checking. INSET: Programmable points.

Focuses on the competition between four companies in the system design and automation industry on system-on-a-chip (SOC) design recognition. Magma Design Automation's place-and-route emphasizing sign-off after synthesis; Monterey Design System's fluid-block design; Sapphire Design Automation's integrated analysis, placement and optimization toolset; Amoeba technology of Silicon Perspective Corp. INSET: ASIC shorts.

Focuses on developments related to embedded memory for SOC design. IBM Microelectronics' introduction of an embedded dynamic random access memory technology; MoSys' launching of its one-transistor SRAM.

Focuses on various tools used to verify system-on-a-chip designs. Verisity's specification-based functional verification technology; Design Acceleration's transaction-based verification test development system; Intrinsix's merger of verification and embedded software development.

Presents an approach to designing a system-on-a-chip. Benefits of merging logical and physical design processes; Complaints about the absence of uniform accessibility among design tools; Diagram of physical interfaces from synthesis to layout.

Focuses on system-on-a-chip (SOC) design. Information on the CoWare N2C design system; Features of the system; Details on the Programmable System Architecture (PSA) of Startup Improv Systems. INSET: An alternative framework for system-on-chip design, by C. Ussery.

Focuses on steps toward static verification in building a system-on-a-chip design. Use of timing analysis; Methods to verify functionality; Leading static timing analysis tool.

Presents datapath synthesis tools in application specific integrated circuits. Use of the Module Compiler (MC) from Synopsis to support a language specifically created for describing datapath design; Terapath datapath-syntheis tool from Tera Systems.

Speculates on the advantages of using application specific integrated circuits (ASIC) libraries for low power tools. Factors why vendors hesitate to support power tools with ASIC libraries; Reasons for defining advanced library format (ALF); Developments made on ASIC library tools.

Discusses the need to link logical and physical design for deep submicron applications specific integrated circuit (ASIC) design. Sun Microsystems' design and construction of a 0.35 micrometer versus the standard 0.5 micrometer ASIC on use; How design engineers are performing synthesis and changing their methodology in designing; Information on floorplanning and place-and-route tools for design. INSET: A checklist for logical to physical links..

Reports that Electronic Design Automation (EDA) vendors and distributors are opening up Application Specific Integrated Circuit (ASIC)/Field Programmable Gate Array (FPGA) design centers and offering field support. Information about the physical design group-Cadence Design Systems of Audio Digital Imaging; Information about Insight Electronics Memec Design Services (MDS); Agreement between Mentor Graphics with David Sarnoff Research Center.

Introduces Eaglei, a product developed for hardware/software coverification and integration from Beaverton, Oregon-based Eagle Design Automation. How the Eaglei lets the user execute the application program on simulated hardware long before the hardware exists; Introduction of Seamless Co-Verification Environment (CVE) by Mentor Graphics; Aptix's system emulation tools.

Praises the various applications of EPIC's simulation-based PowerMill particularly on area/power tradeoffs based on real numbers. Comment of John Hillan of VLSI Design Group of Pacific Communications Sciences, Incorporated on how the company uses the PowerMill; Advantages of working with PowerMill; How the Cirrus Logic produced the read-channel ICs for hard-disk drives.

Describes a number of tools electronic designers can use to develop embedded computer systems that contain as much software as hardware. Example of a reactive real-time embedded system; Polis project with the University of California in Berkeley and Magneti Marelli; Hardware/software codesign toolset from CoWare; Omniview's Performance Modeling Workbench.

Focuses on issues concerning the development of synthesizable core-based design in application specific integrated circuits (ASIC). Challenges in integrating synthesizable cores; Comment by Amjad Qureshi, senior design manager at Samsung Semiconductor; Need for core vendors to give users more documentation; Features of the synthesizable core products offered by vendors. INSET: Testability a tough task, by R. Chandramouli..

Features test-bench tools for application specific integrated circuits (ASIC). Includes Diagonal Systems' BestBench test-bench tools; Chronology's Quickbench visual test-bench generator; OmniView's Alchemist tool. INSET: You'll need a deep toolbox for test benches..

Reports on the emergence of recycling software for porting leaf-cell libraries and chip designs to new processes or foundries. Aspec Technology's QuickPort software and chip-level design portability; Rubicad's LACE layout-conversion and compaction tool; Mentor Graphics' ICGen process-portable module-generation software; Cascade Design Automation's MasterPort design-portability tool.

Evaluates various design of real-time level floorplanners. High Level Design System's (HLDS) Top-Down Design Planner (DP) (RTL) floorplanner; Cadence Design Systems' Silicon Quest front-end floorplanner; Compass Design Automation's ChipPlanner; Estimation and code annotation; Timing numbers; Floorplanning competitors; Timing correlation; Estimate power.

Reports on EPIC Design Technology's release of the full-chip and net-by-net resistance/capacitance (RC) extraction tool developed by Archer Systems for deep submicron called Arcadia. Features; Competition; Pattern libraries; Application in analysis of clock rates; Accounting for neighbors.

Looks at various fast hardware description language-based cycle simulators. Cycle-based simulation in submicron application specific integrated circuits; Mechanism of action of cycle-based simulators; Description of this product type from Cadence Design Systems, SpeedSim and Vantage Analysis Systems.

Features an excerpt of a discussion on emulation and silicon prototyping between Toshiba America Electronic Components' Steve McMinn and Zycad's Bill Portelli. Intel's Pentium; Gates; Large macros; Debugging; Costs; Expectations.

Describes tools from Cadence Design Systems and Quickturn Design Systems for designing system-on-a-chip (SOC) devices. Cadence's Affirma hardware/software coverification tool; Quickturn's VIPER services and rate-adapter products.

Reports on Texas Instruments' movement into a standard-cell flow with system-integration capability. Company's collection of Internet protocol (IP) developed by the company; Integration issue as the challenge to the company.

Reports on the efforts to develop an application specific integrated circuit with hardware and software content. Progress in hardware/software codesign and subset coverification; Applied's CoreTAP ARM7TDMI codevelopment platform; Validation of blocks of final design; Addition of codesign capabilities in Mentor Graphics' Seamless coverification environment.

Reports on Mentor Graphics and Synopsys' joint introduction of the book `Reuse Methodology Manual' written by Mentor's IP Factory Director Pierre Bricaud and Synopsys' Engineering Director Mike Keating. Features of the book; Significance of the move to system-on-a-chip designers.

Focuses on the cooperative efforts of electronic design automation and application specific integrated circuits vendors in the United States to develop standards for system-on-a-chip design. Cadence Design Systems' licensing of application programming interfaces for enhanced versions of its physical library and design data formats; Benefits of the effort to the industry.