279 results on '"Veloso, Anabela"'
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2. Impact of the channel doping on the low-frequency noise of gate-all-around silicon vertical nanowire pMOSFETs
3. High-density standard cell libraries with backside power options in A14 nanosheet node
4. Active area patterning for CFET: nanosheet etch
5. Si GAA NW FETs threshold voltage evaluation
6. Impact of the channel doping on the low-frequency noise of silicon vertical nanowire pFETs
7. Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature
8. On the asymmetry of the DC and low-frequency noise characteristics of vertical nanowire MOSFETs with bulk source contact
9. Design of operational transconductance amplifier with Gate-All-Around Nanosheet MOSFET using experimental data from room temperature to 200 °C
10. Analysis of zero-temperature coefficient behavior on vertically stacked double nanosheet nMOS devices
11. Impact of Sub-$\mu$m Wafer Thinning on Latch-Up Risk in DTCO/STCO Scaling Era
12. Low frequency noise performance of horizontal, stacked and vertical silicon nanowire MOSFETs
13. (Invited) In-Depth Understanding of the Key Contributors to the Total Flicker Noise in Advanced Logic Devices
14. Parameter extraction using the transfer characteristics of vertically stacked Si nanosheet MOSFETs.
15. (Invited) In-Depth DC and Low Frequency Noise Characterization of Nanosheet FETs at Room and Cryogenic Temperatures
16. Produção e composição mineral da batata-doce ‘Lira’
17. Advanced high-voltage e-beam system combined with an enhanced D2DB for on-device overlay measurement
18. Small target compatible dimensional and analytical metrology for semiconductor nanostructures using x-ray fluorescence techniques
19. Impact of Sub-μm Wafer Thinning on Latch-Up Risk in DTCO/STCO Scaling Era
20. Is There a Limit When the Access Resistance Impact on the Extraction of Key Gaa Ns Fets Devices Parameters Can (Not) Be Avoided?
21. 3d Backside Integration of Finfets: Is There an Impact on Lf Noise?
22. Refined DC and Low-Frequency Noise Characterization at Room and Cryogenic Temperatures of Vertically Stacked Silicon Nanosheet FETs
23. Fertilidade do solo e nutrição mineral da 'Batata-doce de Aljezur'
24. Performance Perspective of Gate-All-Around Double Nanosheet CMOS Beyond High-Speed Logic Applications
25. (Invited, Digital Presentation) Innovations in Transistor Architecture and Device Connectivity Options for Advanced Logic Scaling
26. Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation
27. Middle-of-line plasma dry etch challenges for buried power rail integration
28. (Invited) Innovations in Transistor Architecture and Device Connectivity Options for Advanced Logic Scaling
29. Experimental Analysis of Trade-Off Between Transistor Efficiency and Unit Gain Frequency of Nanosheet NMOSFET down to -100 oC
30. On the efficiency of stress techniques in gate-last n-type bulk FinFETs
31. Advanced high-voltage e-beam system combined with an enhanced D2DB for on-device overlay measurement
32. Small target compatible dimensional and analytical metrology for semiconductor nanostructures using x-ray fluorescence techniques
33. Simultaneous Dimensional and Analytical Characterization of Ordered Nanostructures
34. Stress in Silicon–Germanium Nanowires: Layout Dependence and Imperfect Source/Drain Epitaxial Stressors
35. (Invited) Impact of Processing Factors on the Low-Frequency Noise of Gate-All-Around Silicon Vertical Nanowire FETs
36. Impact of Sub-µm Wafer Thinning on Latch-up Risk in STCO Scaling Era
37. High Temperature Influence on the Trade-off between gm/ID and fT of nanosheet NMOS Transistors with Different Metal Gate Stack
38. On the Asymmetry of the DC and Low-Frequency Noise Characteristics of Vertical Nanowire pMOSFETs with Bulk Source Contact
39. Operational Transconductance Amplifier Design with Gate-All-Around Nanosheet MOSFET using Experimental Lookup Table Approach
40. Low temperature investigation of n-channel GAA vertically stacked silicon nanosheets
41. Fertilidade do solo e nutrição mineral da "Batata-doce de Aljezur".
42. Current mirror designed with GAA nanosheet MOSFETs from room temperature to 200 °C
43. Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures
44. Time Evolution of DIBL in Gate-All-Around Nanowire MOSFETs During Hot-Carrier Stress
45. ‘’Batata-doce de Aljezur’‘ - Avaliação da fertilidade dos solos
46. Engineering high quality and conformal ultrathin SiNx films by PEALD for downscaled and advanced CMOS nodes
47. Analysis of the ZTC-Point for Vertically Stacked Nanosheet pMOS Devices
48. Composição mineral dos frutos de cinco cultivares de marmeleiro na região de Alcobaça
49. Effect of SIIS on work function of self-aligned PtSi FUSI metal-gated capacitors
50. (Invited) Stress Simulations of Fins, Wires, and Nanosheets
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