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The critical problem of global wire optimization for nanometer scale very large scale integration technologies and its impact on power dissipation, bandwidth and performance is considered. A novel methodology for optimizing global interconnect width that is used to develop analytical expressions for optimum interconnect widths for figure of merits is presented.

A charge-successive integrator (CSI) VLSI with a wide dynamic range has been developed for the front-end electronics of the Telescope Array project. The CSI has more than a 14-bit dynamic range and successively integrates the charge from a photomultiplier tube every 200 ns. We have newly designed an offset-compensated charge integrator to reduce the offset voltage and the 1/f noise. We expect that the offset voltage and the maximum 1/f noise can be reduced to less than 2 mV and 0.2 [micro]V/sqrt Hz, respectively, with this technique. The prototype CSI chip was fabricated using a 0.6-[micro]m commercially available CMOS technology. The test results of a prototype CSI chip, which has no offset compensation, are compared to the offset-compensated low-1/f noise CSI to confirm the effectiveness of this technique. Index Terms--CMOS integrated circuits, electronics, integrators, switched capacitor circuits.

In this paper, we present a multichannel very large scale integration implementation of ROTOR, a time-variant parameters shaping amplifier designed for the readout of high-rate asynchronous signals from multi-element solid-state X-ray detection systems. In particular, ROTOR was optimized for high-rate X-ray spectroscopy with multi-element semiconductor drift detectors (SDDs) in applications using synchrotron light sources such as X-ray holography or extended x-ray absorption fine structure (EXAFS) experiments. A 30 channels circuit has been implemented in the 1 [micro]m/5 V JFET/CMOS technology of the Fraunhofer-Institut, Duisburg, Germany. Each analog channel features a trapezoidal weighting function, 1.6 [micro]s wide, obtained by means of a switched-current technique. A digital section, directly integrated on the ROTOR chip, allows the timing and control of all the analog switches of the amplifiers as required for the circuit functionality, without the need of external signals. The main features of the circuit design and the results obtained in the experimental characterization of the prototype, also in spectroscopy measurements by using an SDD, are presented. Index Terms--Integrated readout circuits, shaping amplifiers, silicon drift detectors, X-ray spectroscopy.

This paper proposes a low-power very large-scale integration (VLSI) architecture for motion tracking. It uses a hierarchical adaptive structured mesh that generates a content-based video representation. The proposed mesh is a coarse-to-fine hierarchical two-dimensional mesh that is formed by recursive triangulation of the initial coarse mesh geometry. The structured mesh offers a significant reduction in the number of bits that describe the mesh topology. The motion of the mesh nodes represents the deformation of the video object. The architecture consists of a motion estimation and motion compensation units. The motion estimation architecture generates a progressive mesh code and the motion vectors of the mesh nodes. It reduces the power consumption, it uses a simpler approach for mesh construction, approximates the mesh nodes motion vector by using the three step search algorithm and it uses parallel motion estimation core to evaluate the mesh nodes motion vectors. Moreover, it maximizes the lifetime of the internal buffers. The motion compensation architecture uses a multiplication-free algorithm for affine transformation, which significantly reduces the complexity of the motion compensation architecture. Moreover, using pipelined affine units contributes to the power savings. The video motion compensation architecture processes a reference frame, mesh nodes and motion vectors to predict a video frame. It implements parallel threads in which each thread implements a pipelined chain of scalable affine units. This motion compensation algorithm allows the use of one simple warping unit to map a hierarchical structure. The affine unit warps the texture of a patch at any level of hierarchical mesh independently. The processor uses a memory serialization unit, which interfaces the memory to the parallel units. The architecture has been prototyped using top-down low-power design methodology. The performance analysis shows that this processor can be used in online object-based video applications such as in MPEG and VRML. Index Terms--Affine transformation, digital video processing, HDTV, low power architecture, mesh-based motion tracking, motion compensation, motion estimation, multimedia, VLSI.

Modern applications, e.g., very large-scale integration (VLSI) manufacturing, give rise to complicated queueing models, often of the re-entrant type. Their complexity, together with implications of their performance, have renewed interest in their performance and the computation of good control (e.g., scheduling) policies. Recent work concentrated on computable (mostly linear) performance bounds. We show that the linear bounds can be obtained naturally, and under weaker assumptions, using generating function techniques. This approach gives rise to a new class of bounds, on performance over busy periods. Index Terms--Busy period bounds, generating functions, linear bounds, performance, re-entrant lines.

Throughout the decade, Electronic Design Automation (EDA) tools must enable engineers to produce increasingly complex IC and VLSI designs at a fast pace, but with greater built-in manufacturability and testability. […]