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There has been an impressive increase in single-chip processing power since the Intel 4004 was launched in 1971. This is usually attributed to Moore's law, but there are additional factors to consider. In understanding the components of prior improvements, we can gain insight into the potential for future improvements and potential limits to scaling.

Silicon photonics (SiPh) is a disruptive technology in the field of integrated photonics and has experienced rapid development over the past two decades. Various high-performance Si and Ge/Si-based components have been developed on this platform that allow for complex photonic integrated circuits (PICs) with small footprint. These PICs have found use in a wide range of applications. Nevertheless, some non-native functions are still desired, despite the versatility of Si, to improve the overall performance of Si PICs and at the same time cut the cost of the eventual Si photonic system-on-chip. Heterogeneous integration is verified as an effective solution to address this issue, e.g. through die-wafer-bonding and flip-chip. In this paper, we discuss another technology, micro-transfer printing, for the integration of non-native material films/opto-electronic components on SiPh-based platforms. This technology allows for efficient use of non-native materials and enables the (co-)integration of a wide range of materials/devices on wafer scale in a massively parallel way. In this paper we review some of the recent developments in the integration of non-native optical functions on Si photonic platforms using micro-transfer printing.

GaAs on Si grown via metalorganic chemical vapor deposition is demonstrated using various Si substrate thicknesses and three types of dislocation filter layers (DFLs). The bowing was used to measure wafer‐scale characteristics. The surface morphology and electron channeling contrast imaging (ECCI) were used to analyze the material quality of GaAs films. Only 3‐μm bowing was observed using the 725‐μm‐thick Si substrate. The bowing shows similar levels among the samples with DFLs, indicating that the Si substrate thickness mostly determines the bowing. According to the surface morphology and ECCI results, the compressive strained indium gallium arsenide/GaAs DFLs show an atomically flat surface with a root mean square value of 1.288 nm and minimum threading dislocation density (TDD) value of 2.4 × 107 cm−2. For lattice‐matched DFLs, the indium gallium phosphide/GaAs DFLs are more effective in reducing the TDD than aluminum gallium arsenide/GaAs DFLs. Finally, we found that the strained DFLs can block propagate TDD effectively. The strained DFLs on the 725‐μm‐thick Si substrate can be used for the large‐scale integration of GaAs on Si with less bowing and low TDD.

Two-dimensional materials could play an important role in beyond-CMOS (complementary metal–oxide–semiconductor) electronics, and the development of memristors for information storage and neuromorphic computing using such materials is of particular interest. However, the creation of high-density electronic circuits for complex applications is limited due to low device yield and high device-to-device variability. Here, we show that high-density memristive crossbar arrays can be fabricated using hexagonal boron nitride as the resistive switching material, and used to model an artificial neural network for image recognition. The multilayer hexagonal boron nitride is deposited using chemical vapour deposition, and the arrays exhibit a high yield (98%), low cycle-to-cycle variability (1.53%) and low device-to-device variability (5.74%). The devices exhibit different switching mechanisms depending on the electrode material used (gold for bipolar switching and silver for threshold switching), as well as characteristics (such as large dynamic range and zeptojoule-order switching energies) that make them suited for application in neuromorphic circuits. High-density memristive crossbar arrays made from two-dimensional hexagonal boron nitride can be fabricated with a yield of 98% and used to emulate artificial neural networks.

Wafer-scale heterogeneous integration provides a viable pathway for the development of highly capable microsystems. However, it remains challenging to integrate die-and wafer-level components with a high-density interconnects while minimizing the system volume and within the temperature restrictions imposed by integrated circuits. Advancements in CMOS have motivated the development of low-temperature and low-resistance metal–silicon alloys or silicides. Nickel silicide (NiSi) is a CMOS-compatible material that forms at temperatures and anneal times within the thermal budget of commercial CMOS die and can be implemented with a wide range of nickel and silicon thin-film processing methods. We describe here the development of a 3-D integration strategy utilizing NiSi formation to generate both mechanical bonding and electrical interconnection between wafers. Specifically, we show that our NiSi-based wafer-bonding process is effective below 400 °C, at very short anneal times (minutes), and with a variety of thin-film processing methods. This NiSi-based process offers a robust approach for creating heterogeneously integrated microsystems in a CMOS-compatible fashion.

Organic semiconducting polymers have opened a new paradigm for soft electronics due to their intrinsic flexibility and solution processibility. However, the contradiction between the mechanical stretchability and electronic performances restricts the implementation of high-mobility polymers with rigid molecular backbone in deformable devices. Here, we report the realization of high mobility and stretchability on curvilinear polymer microstructures fabricated by capillary-gradient assembly method. Curvilinear polymer microstructure arrays are fabricated with highly ordered molecular packing, controllable pattern, and wafer-scale homogeneity, leading to hole mobilities of 4.3 and 2.6 cm2 V−1 s−1 under zero and 100% strain, respectively. Fully stretchable field-effect transistors and logic circuits can be integrated in solution process. Long-range homogeneity is demonstrated with the narrow distribution of height, width, mobility, on-off ratio and threshold voltage across a four-inch wafer. This solution-assembly method provides a platform for wafer-scale and reproducible integration of high-performance soft electronic devices and circuits based on organic semiconductors., Though stretchable semiconducting polymers are advantageous for electronic applications requiring low cost, the low performance of patterned microstructures remains a challenge. Here, the authors realize high mobility, stretchable polymer microstructures via a capillary-gradient assembly method.

Au/Ta/Ti metal multilayer was developed for the improved vacuum packaging process. Wafer-level packaging after degas at 200 °C and absorbing gas molecules at 300 °C were successfully demonstrated using this multilayer. The activation temperature for gas gettering was lower than that of previous studies using the Au/Pt/Ti layer.

According to Moore's Law, the wafer level packaging and fan-out packaging market is expected to witness a compound annual growth rate (CAGR) of 18% during the forecasted period (2021 – 2026). And there are also some challenges for the high speed plating technology in the production of wafer level advanced packaging. Recently after a long time development, ACM announces high-speed copper (Cu) plating technology, which is now available for its ECP ap system. The tool supports Cu pillar bumping for copper(Cu), nickel (Ni) and tin-silver (SnAg) plating. The unique paddle design enables the new high-speed electroplating technology to support the copper electroplating chamber with a stronger mass transfer capacity during the electroplating process. Also, the channel of diffusion layer becomes shorter and the diffusion efficiency of cation is improved. The second anode well control the electric field the distribution of cations on the wafer surface, and with the paddle stirring action, the cathode polarization phenomenon is reduced, which improved the electroplating efficiency and effectively reduced the boundary layer thickness to ensure the electroplating quality. Not only does it perform well in electroplated copper pillars, it can still maintain good uniformity and coplanarity in the electroplating of oversized bumps with higher aspect ratios and more stringent requirements for electroplating speed. The test results of ACM Ultra ECP ap series equipment meet the requirements of high speed volume production and the uniformity is also at leading edge level.

It's believed that 3D integration technology is a solution to beyond More-than-Moore law and to bring incremental cost-power-performance value. An advanced 3D dislocation multi-stack integration structure by fan-out wafer-level packaging has been developed for 3D integration. Four ultra-thin NAND Flash chips which thickness is about 40um can be integrated by Package-on-Package (PoP) method. The package size is ${18\text{mm}\times 12}$ mm ${\times 0.89\text{mm}}$ , and BGA pitch is 1mm. The 3D dislocation multi-stack integration technology can be used as an alternatives solution to wire bonding and through-silicon-via (TSV) technology for NAND flash packaging.

Wafer level packaging is one of the latest trends in microelectronic packaging. Wafer warpage and metal peeling are common problem in wafer level packaging. Large warpage and large area peeling will cause the failure of post packaging and reliability problem. The mechanism of warpage and stress are the mismatch of material's coefficient of thermal expansion (CTE) and the change of temperature in the process. In this paper, after plating a metal layer on passivation (PA) layer, there is a large wafer warpage, which makes the following process unable to continue. Based on this background, plating a metal layer on the back side of wafer is innovatively proposed to overcome warpage. The warpage and peeling of back side metallization (BSM) are also measured. The experiment also compares warpage with and without BSM. The reason of peeling, the location of peeling and the interface of peeling were studied by experiments. Based on the finite element analysis (FEA). The effect of different BSM masks on warpage and peel stress were studied. The effects of local design and BSM thickness on peel stress are also studied. Through the research of this paper. It provides guidance for the metal plating process and design of BSM, and can effectively overcome the problem of wafer warpage and peeling.

Silicon nanowire (SiNW) biosensors have received a special attention from the research community due to its ability to detect a range of species. The nano feature size of the SiNW has been exploited to fabricate small, low-cost, robust, portable, real-time read-out biosensors. These sensors are manufactured by two methods – top-down or bottom-up. Instead of the bottom-up method, the top-down approach is widely used due to its compatibility with complementary metal-oxide semiconductor (CMOS) process and scope of mass production. However, in the top-down method, the post fabrication microfluidic channel integration to access the SiNW test site remains complex and challenging. Since the nanosensor is expected to operate in a bio environment, it is essential to passivate the metal electrodes while pathways have to be made to access the test site. In this paper, we present a relatively easier method to access the SiNW test site without employing complex microfluidic channels while achieving leakage free passivation of metal electrodes and preserving the integrity of the nanosensor. This is accomplished in the last step of the manufacturing process by employing a lithography mask and reactive ion etching (RIE). HfO2 integrated crystalline silicon nanosensors are manufactured using novel top-down front end of line (FEOL) sidewall transfer lithography (STL) process. HfO2 acts as an etch stop layer while performing RIE in the last step to access the sensor test site. The 100 mm wafer scale results of 20 nm × 60 nm × 6 μm (H x W x L) p-type nanosensors shows an average Ion/Ioff ≥ 105 with maximum turn-on voltage of −4 V and uniform subthreshold slope of 70 mV/dec. In comparison with sensors encapsulated with SiO2, the HfO2 integrated nanosensors were found to improve the threshold voltage variation by 50%. Based on this work, the HfO2 integrated SiNW demonstrates good stability for biosensing application.

A novel defect-tolerant network of digital-to-analog converters (DACs) is presented in this paper. The architecture of this converter employs a single 2.5-V voltage reference and an unbalanced buffering technique to achieve a wide voltage range that extends from 864 mV to 2.538 V with an 8-bit resolution. The proposed converter incorporates a defect-tolerant architecture and is extremely compact, utilizing a per-bit silicon area of less than 350 $\mu \text{m}^{2}$ . Although such very small area allows for embedding in dense configurable fabrics (field-programmable gate arrays) and wafer-scale integration, the overall performance is not sacrificed as reported measurements show a signal-to-noise ratio of 51.87 dB and a spurious-free dynamic range of 42.31 dB, at 10 MS/s providing 7.6 effective bits. Moreover, the proposed architecture benefits from dynamic calibration capabilities, as any converter output can be finely adjusted over a range of 25 mV. This proposed DAC is also extensively reused in the same defect-tolerant network for a successive approximation register-analog-to-digital converter, as well as for a configurable voltage reference.

In order to fabricate a wearable flexible display as a flexible hybrid electronic (FHE) device with micro-LED dies, we demonstrate multi-level metallization on an elastomer using die-first fan-out wafer-level packaging (FOWLP). The elastic substrate of this display is PDMS (polydimethylsiloxane) in which the array of 3-color micro-LEDs is embedded. In this study, we address serious issues such as die shift and stress accumulation in advanced FOWLP to integrate a self-luminescent flexible micro-LED display.

More recently, "chiplets" are expected for further scaling the performance of LSI systems. However, system integration with the chiplets is not a new methodology. The basic concept dates back well over a few decades. The symbolic configuration of this concept based on the chiplets is 3D integration with TSV we have worked on since 1989. This paper introduces our 3D and heterogeneous system integration research from its historical activities to the latest efforts, including capillary self-assembly of tiny dies with a size of less than 0.1 mm and advanced flexible hybrid electronics (FHE) using fan-out wafer-level packaging (FOWLP).

Fan-out Wafer Level Packaging (FOWLP) is expected to become an indispensable platform for integrating heterogeneous chips into advanced semiconductor packaging for next generation edge computing, automotive and others. In order to integrate multiple memory and logic chiplets, the line/space (L/S) design rule of the Cu redistribution line (RDL) will be scaled below $2/2\ \mu\mathrm{m}$ in order to accommodate the multiple chip configurations and high I/O count. While the current semi-additive process (SAP) used to manufacture the 1st generation of FOWLP technology has served the IT industry well, the absence of a physical diffusion barrier between the Cu and the polymer and the heavily undulated topology presents serious reliability and processing challenges. To overcome these limitations, this paper presents the first work published on fabrication of polymer damascene RDLs. RDLs were fabricated by dry-etching patterns into a polymer film, filled with electroplated Cu and planarized with CMP. The use of a Ti diffusion barrier prevents Cu migration into the polymer and the CMP process prevents any unwanted undulation that can adversely affect the line width uniformity. By developing a damascene integration scheme without the use of spin-on hardmasks and bottom anti-reflective coatings, we can keep the costs low without sacrificing the benefits of the damascene structure. Results show well defined RDLs with a robust Ti barrier limiting the diffusion of Cu into the polymer even after wafer level high temperature storage (HTS) testing. With the available technology, this integration scheme has the potential to extend the FOWLP design rule to well below $\mathrm{1}\ \mu\mathrm{m}$ .

A elegant extremely flexible Fan-Out Wafer-Level Packaging (FOWLP) based fully integrated bipolar multi-channel (up to 12 channels) surface electromyography (sEMG) device and assembly is demonstrated for intraoperative neurological monitoring (IONM) for complex spine surgeries and post-op physiological monitoring. It includes twenty gold-capped vertically corrugated flexible dry copper electrodes, Bluetooth wireless data transfer, a multichannel sEMG data acquisition and processing dielet, rechargeable energy storage and an ergonomic reusable adhesive for ease of use. This completely biocompatible and wearable system is highly flexible, thin (1 mm), light weight (< 5 g) and can be used to monitor neuro-muscular activations for IONM as well as for general physiological monitoring.

Heterogeneous Integration is evolving to acquire finer resolution and larger devices to leverage the advantages provided by More-than-Moore manufacturing and packaging technologies that can help maximize the efficiency and increase the bandwidth of high performance computing systems. Advanced Packaging with submicron Redistribution Layers (RDL) and large package sizes is one of solutions that can help enable complex Heterogeneous Integration designs for applications including Artificial Intelligence (AI), 5G communication and autonomous driving. For systems requiring large package sizes, Panel Level Packaging (PLP) can offer efficiency and cost advantages over Wafer Level Packaging (WLP). PLP however poses unique technical challenges including the requirement to realize uniform submicron patterning across the entire rectangular panel. To meet this challenge, Canon developed the first patterning exposure tool or stepper that is capable of submicron resolution on 500 mm panels. This new panel exposure tool is equipped with wide-field projection optics that offer a large $\mathrm{52}\ \text{mm}\times \mathrm{68}\ \text{mm}$ image field and 0.24 NA that is optimum for submicron resolution. The stepper also features a newly developed panel handling system for processing up to $\mathrm{515}\times \mathrm{515}\ \text{mm}$ panels. In this paper, we will report on evaluation results of fine patterning for a mass-production panel level packaging process using the new submicron resolution panel stepper. We will also discuss current fine-PLP status, challenges and solutions. One topic of our study is patterning uniformity. In 2020, we reported patterning uniformity improvement technology using a glass substrate. This study attempts to apply the technology described in 2020 to improve pattern uniformity on Copper Clad Laminate (CCL) substrates that are widely used in printed circuit board (PCB) manufacturing. In addition, we will report on results of studies of stitching capability and alignment accuracy on substrates with die placement error. Our study also explored warped panel handling including the development of a multi-vacuum line chucking system.

Fan-out wafer-level packaging (FOWLP) has evolved from chip-scale packaging to be one of the enablers of heterogenous integration through chip-first or redistribution-layer (RDL)-first processes, which draw significant momentum in packaging industries to develop newer and better materials. Among all of the essential packaging materials currently being investigated, novel laser release materials are of particular interest because they are vital to the successful separation of reconstituted wafers and glass carriers. Thus, the thermal, chemical, and mechanical stability of the laser release material play a vital role for success in FOWLP integration. In this study, four laser release materials with UV-light absorbance were evaluated through experiments divided into two phases to select a champion material for chip-first and RDL-first FOWLP integration. Phase I consisted of the collection of material properties and characteristics including light transmittance, interaction with laser energy, thermal stability, adhesion, and melt rheology to determine compatibility with RDL-first and chip-first processes, respectively. In Phase II, all candidate laser release materials were introduced to a short-loop evaluation that started with a laser release material coating on 300-mm glass carrier with a coefficient of thermal extension (CTE) of 8 ppm/°C, followed by 50-nm titanium deposition, 100-nm copper deposition, and dielectric material coating before encapsulation with epoxy molding compound. Multiple 355-nm laser powers that created different diameters of effective ablation region inside the crater, were used to determine the sensitivity of each candidate material. Meanwhile, chips sized, were picked and placed on coated glass carriers with candidate laser release materials to evaluate the compatibility with the chip-first process. Finally, design of a die bonding experiment was used to summarize the optimal conditions of a laser release material, proved compatible with RDL-first in advance, for a chip-first process. Through the comprehensive material evaluation discussed in this study, optimal laser release materials for the RDL-first and chip-first processes are identified. Of particular interest are materials that possess both laser release properties and good adhesion, since their use in die bonding applications will enhance throughput and lower the cost of ownership for FOWLP.

Hybrid bonding or surface activated bonding is becoming a very attractive technology to manufacture higher performance CMOS by addressing pitch scaling difficulties of solder interconnects. One of the major challenges for dielectric bonding is to decrease the process temperature to be compatible with CMOS processing. Many investigations have demonstrated low bonding temperatures (annealing temperatures below 250°C) with either SiCN or SiN. In this paper, we focus on the dielectric layer deposition process. Both low temperature physical vapor deposition (PVD) of SiN and SiCN are investigated side by side. Film stress as function of film thickness is characterized to understand its potential impact on wafer warpage. Reliability of low temperature SiN film is tested on both inorganic and organic surfaces so it can be leveraged in a wide set of wafer level packaging applications.

Advances in the high performance computing (HPC) lead to a new frontier of the fan out wafer level packaging (FOWLP) development. To provide a solution of cost-attractive package for heterogeneous chip integration, FOWLP has recently emerged as an indispensable platform. Herein, we propose novel 2.5D re-distribution layer (RDL) interposer packaging technology including the fabrication of fine-pitch RDL interposer (>560 mm2) assembled with one high-bandwidth memory (HBM) and two ASICs, in order to achieve the TSV-less and cost-effective package. The intrinsic features of the fine-pitch RDL interposer enhances the integrity of the signals and the reliability of the bump joints, and thus integrates multiple chips and accommodates higher I/O counts. With the fine-pitch 2.5D RDL interposer technology, the system-in-package is fabricated in order to substantiate the functions of the HBM, and tested to analyze the characteristics of its performance. The fine-pitch 2.5D RDL interposer package demonstrates up to 3.2Gbps/pin operation with the HBM, and also shows excellent reliability without any failure during the reliability tests (TC1000hr, b-HAST 264hr, u-HAST 264hr and HTS1000hr). The proposed 2.5D RDL interposer technology can be a promising solution for the cost-effective and large size 2.5D packaging in the HPC applications.

Intel's Embedded Multi-die Interconnect Bridge (EMIB) technology is an advanced, cost-effective approach to in-package high density interconnects of heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths between multiple dice in a package. This technology uses local silicon bridges to host ultrafine line / space structures for die-to-die interconnect communications and opens avenues for heterogeneous chip integration applications. In EMIB package architecture, a silicon bridge die is embedded into an organic substrate, encapsulated with dielectric materials, and connected to external layers of package substrate through semi additive substrate build-up processes at the panel level. Many bridge dice can be embedded as part of the high-density interconnect package substrate fabrication process. Afterwards, logic or heterogeneous dice (Chiplets of various nodes / sources, HBMs, IO tiles, etc.) are bonded to EMIB substrates through assembly process, with EMIB bridges serving as a high-bandwidth, low-latency, and low-power solution for die-to-die communications, thereby enabling a low-cost, highperformance in-package heterogeneous chip integration solution. Simply put, EMIB employs a silicon piece that hosts ultrafine line / space structures, fabricated with silicon far-backend technology, but out of Intel's high-density interconnect package substrate manufacturing infrastructures and capabilities. One of the key elements of EMIB advanced packaging technology is to embed the EMIB bridge dice reliably during the substrate fabrication process. As such, an overview of the general technical challenges associated with panel level EMIB die embedding will be presented in this paper as compared to the industry standard wafer level packaging (WLP) die embedding process.

Lead-free soldering materials have been of great interest in the field of advanced microelectronic packaging during the last decade. Compared to the eutectic tin-lead solder (Sn-Pb), the increased melting temperature influences mechanical properties that can compromise the integrity of the solder joint in a long period of working time. In the present work, a two-dimensional (2-D) Fan out Wafer Level Packaging structure was modelled with SAC305 for the soldering material. Anand creep model was utilized for the solder balls using different solder interconnect material properties determined for SAC305 taken from different literature sources. The 2-D model of the package was subjected to a cyclic thermo-mechanical load. The primary outcomes of creep behavior were studied using implicit visco-plastic analysis for the solder. Equivalent of Creep Strain (ECS), and Total Equivalent of Creep Strain (TECS) history showed different results for the various parameter sets of the same solder. Since SAC305 is one of the most widely used lead-free soldering materials, for simulation purposes, researchers must rely on the material properties obtained from experimental results. In this study, a more general view is presented regarding SAC305 visco-plastic properties.

We demonstrated that Au/Pt/Ti (from top to bottom) metal multilayers enables wafer-level packaging of degassed assemblies and residual gas gettering. A hermetic sealing was fabricated by Au surfaces after degassing annealing at 200°C. In addition, the Ti underlayer atoms diffused to the internal surface by annealing at 450°C, enabling the gas in the package. As the Au/Pt/Ti layers have the functions of the bonding layer and gas getter, the proposed packaging technique can potentially simplify a vacuum sealing process.

High performance infrared focal plane arrays (FPAs) play a critical role in a wide range of imaging applications. However the high cost associated with the required cooling and serially processed die-level hybridization is major barrier that has thwarted Mid-wavelength Infrared (MWIR) detector technology from penetrating largevolume, low-cost markets. Under the Defense Advanced Research Projects Agency (DARPA) WIRED program, the HRL team has developed a wafer level integration schemes to fabricate large format Antimonidebased MWIR FPAs on Si Read Out Integrated Circuit (ROIC) as a means to achieve significant fab cost reduction and enhanced production scalability. The DARPA-hard challenge we are addressing is the thermal and stress management in the integration of two dissimilar materials to avoid detector and ROIC degradation and to maintain structure integrity at the wafer scale. In addition, a digital ROIC with extremely large well capacity was designed and taped-out, in order to increase the operating temperature of the FPAs. In this talk, we discuss our progress under the DARPA WIRED program.

The physical limit of traditional CMOS process is approaching, and the progress of processes and devices has become the key problem to the development of microprocessor technology in the post exascale computing era. In this paper, the traditional CMOS process, packaging process and new principle devices are prospected, and the current situation and development prospect of various processes and devices are analyzed. Firstly, the development trend of CMOS process in transistor structure, integration and power consumption is analyzed; Secondly, 3D packaging, 2.5D packaging, chiplet, thruchip interface and wafer scale integration technologies are analyzed; Finally, the negative capacitance transistors, tunneling transistors, two-dimensional semiconductor transistors, carbon nanotube transistors and compute-in-memory technologies using phase change memory and resistive memory are analyzed.

Temporary bonding (TB) and debonding (DB) of wafers have been widely developed and applied over the last decade in various wafer-level packaging technologies, such as package-on-package (PoP), fan-out integration, and 2.5D and 3D integration using through-silicon vias (TSVs). The materials used to achieve TB and DB are extremely critical and the industry's current best practice is the use of two layers of materials (bonding layer and release layer). In this paper, a novel single-layer adhesive is presented to possess both functions of TB with mechanical DB. The properties of this material empower the capabilities of handling ultrathin wafers, supporting very low warpage for high-stress substrates, and surviving high-temperature processing. Testing on a blank silicon wafer thinned down to 20 µm showed neither defects nor edge chipping. In addition, a thermal simulation of 250°C for 30 minutes also passed qualification. Less than 30 µm warpage on an 8” wafer was also observed, which proves the material is friendly to high-stress substrates. More importantly, using fewer layers means fewer total processes, fewer cleaning steps, and lower cost of ownership.

In this paper, a multilayered integrated inductor in Fan-out Wafer Level Packaging (FoWLP) technology is investigated. The inductor is designed on polyimide for integration into the redistribution layer of the package. Excellent correlation is obtained between simulation and measurement results. The fabricated inductor has an inductance of approximately 480 pH and a quality factor of approximately 27 at 11 GHz.

The Fan Out Wafer Level Packaging, widely used in the silicon semiconductor system, is introduced for all-in-one hybrid optical package with small form factor, potentially higher performance, and expendability to on-board/co-packaged optical interconnections. To prove the new packaging idea, 100GBASE-SR4 standard is targeted in this demonstration.

As the focus of graphene research shifts from fundamental physics to applications, the scalability and reproducibility of experimental results become ever more important. Graphene has been proposed as an enabling material for the continuing growth of the telecommunications industry due to its applications in optoelectronics; however, the extent of its adoption will depend on the possibility to maintain the high intrinsic quality of graphene when processing it using the industry-standard approaches. We look at the challenges of scalable graphene integration and the opportunities presented by the recent technological advances.

Double gated WS 2 transistors with gate length down to 18 nm are fabricated in a 300mm Si CMOS fab. By using large statistical data sets and mapping uniformity on full 300mm wafer, we built an integration vehicle where impact of each process step can be understood and developed accordingly to enhance device performance. In-depth analysis of V T variability reveals multiple possible sources at different length scales, with the most prominent one being the channel material. The work presented here paves the way towards industrial adoption of 2D materials.

Industry is constantly looking at ways to reduce the cost of manufacturing. One of the common cost reduction methods is to increase the size of the substrate. The wafer size was increased previously from 6″ to 8″ and then from 8″ to 12″ to increase the number of dies per wafer. The increase in die population per wafer improves the throughput of the processes and hence, reduces the manufacturing cost. Industry is looking towards moving from round wafer to square or rectangle panel in order to further increase the number of dies per substrate. The panel size evaluated in this work is of dimension. The die size usedis with up to 4000 solder bumps. We have developed the RDL 1st Fab-Out Panel-Level Packaging on size panel. The panel size evaluated in this work is of $550\text{mm}\times 650\text{mm}$ dimension. The die size usedis $10\text{mm}\times 10\text{mm}\times 0.7\text{mm}$ with up to 4000 solder bumps. We have developed the RDL 1st Fab-Out Panel-Level Packaging on $550\text{mm}\times 650\text{mm}$ size panel.

The Fan-out wafer-level packaging technology is an integrated circuit technology as well as an enhancement of standard wafer-level packaging (WLP) solutions. This technology is an attractive packaging approach for mobile applications and heterogeneous integration. It allows better electrical performance, low form factor and at relatively low cost as compared to wafer to wafer stacking or 3D stacked bonding. Furthermore, as the industry moving towards higher density and higher-bandwidth chip to chip interconnections, the application of Package on Package technology offers a solution for applications processors and mobile applications with better thermal and electrical performance. One of the significant advantages of package-on-package FOWLP is the ability of stacking 2 different packages to achieve multi-functionality. However, the overall package has to maintain a low profile for thin portable applications. The work in this paper focus on the development and process of wafer level solderball placement on a molded wafer using RDL-first FOWLP process. The Fanout molded wafer is 0.47mm thick and the package size is after singulation. The work in this paper focus on the development and process of wafer level solderball placement on a molded wafer using RDL-first FOWLP process. The Fanout molded wafer is 0.47mm thick and the package size is $15 \times 15\ \mathbf{mm}^{2}$ after singulation. Detailed process parameters on flux printing process parameters such as the printing speed and printing gap coupled with ball placement speed, ball dispense gap and ball head moving direction needs to be evaluated to achieve robust wafer level solderball placement process with good flux printing and good ball placement process yield.

Today's consumers are looking for powerful, multifunctional electronic devices with unprecedented performance and speed, yet small, thin and low cost. This creates complex technology and manufacturing challenges for semiconductor companies as they look for new ways to achieve greater performance and functionality in a small, thin, low cost device. JCET is an industry leader in Wafer Level Packaging (WLP) technology, providing a comprehensive portfolio of WLP solutions including Fan-in Wafer Level Packaging (FIWLP), Fan-out Wafer Level Packaging (FOWLP) and Integrated Passive Devices (IPD This paper shares data and results from our labs and those of our technology partners which come from two recent tube technology advances, both show great potential for providing solutions to the issues of imaging small features quickly, faced in the higher end semiconductor manufacturing industry. Metal Jet Technology, in metal jet anode microfocus xray tubes the traditional solid metal anode is replaced with a jet of liquid metal, which acts as the electron-beam target, The metal jet supports higher electron-beam power and can therefore generate higher X-ray flux. The major benefit of the increased power density level for the metal-jet X-ray tube is the possibility to operate with a smaller focal spot, say 5 ?m, to increase image resolution and at the same time acquire the image faster, since the power is 10x higher for same spot size. Which means that a 5μm spot on a Metal Jet can tolerate approximately 5x higher power compared to a 10μm spot on a tube with a traditional solid filament This technology delivers one of the smallest and most intensive X-ray beams of any Xray source to meet the ever-increasing technology demands, including wafer level package inspection. Nano Tube Technology This enables industry-leading resolution in geometric magnification, the Nano tube is based on advanced electron optics and the latest tungsten-diamond transmission target technology. Automatic e-beam focusing, and astigmatism correction ensures that the smallest possible, truly round spot is achieved. The Nano tube also has the unique feature of internally measuring and reporting the current spot size. In addition, advanced cooling and thermal design results in extreme stability over time. This enables an unprecedented true resolution of 150 nm lines and spaces. The true round spot of the tube is demonstrated by the highly symmetric images of a ‘Siemens star’ resolution target, the innermost features are 150 nm

Semiconductor and Semi equipment industries expect to see a strong upturn in the next few years, with advanced packaging technologies a significant beneficiary of the markets strength. 5G, AI, Edge Computing, Persistent Memory, Integrated Power Management, and the transition to sub 5nm silicon technology are all driving the need for innovative packaging solutions. These solutions integrate silicon produced with disparate process nodes and deliver maximum performance at optimal cost. Heterogeneous Integration, utilizing a multitude of interconnect methodologies (from Fan-out to Silicon Interposer, to Chiplet), addresses this challenge but requires unique solutions for efficient, cost effective die placement. High speed, high precision multi-die placement, directly and efficiently extracted from a range of different sized wafers, is critical to enable cost effective assembly. This paper looks at the challenges and potential approaches for efficient and cost effective solutions.

High-Performance Computing (HPC) systems increasingly adopt Heterogeneous Integration (HI) technologies that utilize large substrates and high-resolution processes to facilitate die and chiplet. Fan-Out Wafer Level Packaging (FOWLP) and silicon interposers using high-density Redistribution Layers (RDL) can help maximize bandwidth and performance but HI roadmaps require improvements in resolution and lower costs to enable wide adoption of these More-than-Moore technologies. Panel based processes can provide cost advantages compared to wafer processes for fabrication of large interposers and Fan-Out packages. Panel based SiP processes however demand submicron resolution over a large field size and uniform exposure across large panels. To meet these challenges, Canon developed the first lithography exposure system capable of achieving submicron resolution on large panels. The new panel exposure tool targets 0.8 μm design rules and utilizes a new panel handling system and stage that allows processing of panels as large as 515 × 515 mm. The new panel exposure tool is equipped with a UL82 wide-field projection lens with a maximum Numerical Aperture (NA) of 0.24 and offers a 52 × 68 mm exposure field for large device fabrication without stitching adjacent shots. Fine-RDL lithography systems must provide a large Depth-of-Focus (DoF) to maintain pattern fidelity to maximize DoF, the new panel exposure tool applies die-by-die focus and tilt compensation and functions to compensate for panel warpage. Process factors related to DoF include panel flatness and photoresist materials and film uniformity. This paper details test results from a panel exposure system that confirms the feasibility and advantages of submicron panel processes. We also introduce additional challenges related to panel processes including slit-coater uniformity, photo resist materials and panel flatness. We will present data illustrating that new panel exposure tool can provide excellent resolution across large exposure fields on panels to enable HI innovation.

What approaches are available for the flip of devices prior to die bond when the top wafer surface cannot be touched? Conventional 180 degree flip on a chip by chip basis during the die sort process requires rubber vacuum pick-up tools to touch both the top and bottom surfaces of device during the required transfers from one pick-up tool to another. However, for a growing number of applications ranging from medical devices, imaging sensors, MEMS, and bumped die used in flip chip applications, touching the sensitive top surface of a device is not desirable, while the need to flip the device remains. Factors to be evaluated in seeking a successful invert process without top surface contact include throughput, wear resistance of tooling, device and tooling material properties, and risk for top surface damage (yield). A pick and place process using an edge gripper instead of vacuum pick-up tip allowed for no contact of device surface but did not provide a robust device flip process due to imprecise device positioning. However, a non-surface contact approach to protect surface features was able to be achieved by using a radius/channel style pick-up tool to pick the die from the wafer and deposit onto a die inverter arm with vacuum surface contact pick-up tool to hold the device in place from the bottom with vacuum. This arm then rotated 180 degrees to place the device into a second radius/channel style pick-up tool, with the tool touching two of the top edges only. Based on the radius design of the channel style tools, the die protruded past the face of the tool, allowing it to be repicked by the main pick-up tool and then subsequently placed to the output. This non-contact approach was found to successfully protect the device surface during the flip. Future research will focus on improving precision of edge grippers so they may also be a potential solution, as well as the testing of the radius/channel pick-up tip approach for applicability with thin devices.

With the economics of transistor scaling no longer universally applicable, the semiconductor industry is turning to innovative packaging technologies to support system scaling and functionality demands while achieving lower system cost. However, high-density packages such as fan-out wafer-level packaging (FOWLP) bring design challenges that traditional organic laminate processes and design tools struggle with and often fail to satisfy. In this paper, we address the challenges that FOWLP and similar high-density advanced packaging (HDAP) technologies bring to designers, outsourced semiconductor assembly and test (OSAT) suppliers, and foundries, and explain why traditional design processes, flows and even design tools struggle and often fail to achieve high-volume production. We discuss the innovative processes and design techniques that must be adopted not just to comply with design requirements, but to do so in a reliable, productive way to achieve high-quality results that meet manufacturing volume yield expectations. We discuss the processes and design flow Mentor developed through partnerships with leading foundries and OSATs, and how they are being used to drive high-volume production.

Wafer level encapsulation has become increasingly important to build up components for mobile and high-performance computing applications. Ranging from system-in-package and antenna modules to high band-width memory device, many of those wafer-level applications demand new features from encapsulant materials. Besides to provide mechanical protection, new wafer-level encapsulants are preferred to bring in extra features: a) reducing package warpage during wafer-level processing; b) being EU REACH compliant, c) showing excellent flowability for trench-fill or gap-fill. In our new material development, these new features can be achieved in a new type of filled epoxy system. The new class of encapsulants maintains high glass transition temperature (Tg), at the same level of typical semiconductor encapsulants, while demonstrating low-warpage during the wafer-level process, an estimation of more than 50% improvement from typical encapsulants. Owing to the use of fine fillers and new resin chemistry, fine gap-filling is possible. Combination of low-warpage and good flowability allows us to serve better in wafer-level applications. Some case studies will be discussed, including: 1) using liquid compression molding (LCM) process to encapsulate the wafers that have built-in trench-gaps, fine-gaps, or solder-bumps. 2) using stencil printing process to encapsulate trenched wafers. In both process routes, low-warpage, void-free gap-fill can be achieved from the packages. Moreover, the encapsulated test-vehicles passed JEDEC MSL-1 reliability conditions. The results demonstrated that this new wafer-level encapsulants have the potential to meet the growing demands from various wafer-level applications.

Compression molding was developed and introduced by Towa in the early 2000s.Over the years, TOWA has continued to improve and enhance the performance and quality of compression molding and, as a result, it has been adopted for complex packaging solutions, especially those requiring low pressure or very thin molded packages. The ever-increasing demand for integration of different technologies and smaller and thinner footprint continues to march forward. These demands challenge mold compression technology to be further expanded and innovated to address even more complicated packaging requirements such as multi-die in large panel format. In parallel, quality and reliability while meeting these challenges for FOWLP in large panel are also considered in this paper. At present, FOWLP has been targeted for high-end products such as High-Performance Computing (HPC)/ Artificial Intelligence (AI) products using RDL-first / high-precision flip chip bonding process with thinning lines and increasing number of IOs. Furthermore, FO-PLP has become a low-end product target, and chip-first cost reduction is in progress. This paper will discuss the concerns & solutions created by compression molding for panelization to address its growing demand. Compression molding is also discussed as a solution to MUF (Mold Under-fill) associated with flip chip bonding due to the use of a degassing process that employs a highly airtight and high vacuum system, and the ability to dispense resin to the full molding area to suppressthe XY flow of resin during molding. In addition, since the structure is such that the force of the press is directly transmitted to the resin, the range of applicable pressure is wide and it is very effective especially for low pressure molding and particularly for fragile elements and ultra-thin interposers. These characteristics are very effective in the RDL-first process by providing a redistribution layer on the carrier, and helping in the suppression of warpage.

In the next few years, advanced process technologies in advanced packaging fabs will migrate rapidly to reduction lithography to achieve 2/2 RDL and beyond. Reticle enhancement techniques, such as Optical Proximity Correction (OPC) may be required in multiple reticle layers to provide sufficient process latitude for high volume manufacturing. However, a challenge in the manufacturing of OPC reticles is the lack of a precise specifications for defect inspection with respect to the printability on wafers [1]. In this paper, the printability of reticle defects for 2/2 micrometers Redistribution Layer (RDL) design rule are studied via i-line resist process. The reticle defect printability is determined by considering the wafer process critical dimension (CD) variability. In the experiment, an i-line 2x reduction stepper with 0.1 NA imaging lens was used to expose the programmed defect reticle. The resist CD response to the reticle defect area is measured under a variety of process conditions, i.e., different exposure dose or focusThe programmed defect reticles consisted of both Clear and Dark Field polarities comprising of 2/2 design rules will be used for the printability study. Defects such as intrusions and protrusions at various sizes on RDL patterns, have been characterized. Defect disposition comparing reticle to designed programmed defects to those without will be shown as well as the impact of the defect on patterning performance. Finally, the allowable reticle defect requirement is assessed where the printable reticle defect size is tied to the wafer process specifications and the actual wafer process CD controllability. The influence of the reticle manufacturing processes on wafer patterning performance is examined. Through this comparison, insights into target specifications (MTT, CDU, defects) for advanced RDL reticles can be derived while balancing cost tradeoffs.