1. An Analog Neural Network Computing Engine using CMOS-Compatible Charge-Trap-Transistor (CTT)
- Author
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Du, Yuan, Du, Li, Gu, Xuefeng, Du, Jieqiong, Wang, X. Shawn, Hu, Boyu, Jiang, Mingzhe, Chen, Xiaoliang, Su, Junjie, Iyer, Subramanian S., and Chang, Mau-Chung Frank
- Subjects
Computer Science - Emerging Technologies ,Computer Science - Hardware Architecture ,Computer Science - Machine Learning - Abstract
An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog-digital interfaces. Through implementing the sequential analog fabric (SAF), the engine mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 784 by 784 CTT computing engine is implemented using TSMC 28nm CMOS technology and occupied 0.68mm2. The simulated performance achieves 76.8 TOPS (8-bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem -- classifying handwritten digits on MNIST database and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution., Comment: 9 pages, 11 figures
- Published
- 2017