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We measure the Casimir force gradient between silicon surfaces with nanoscale, rectangular corrugations and a gold sphere attached to a micromechanical torsional oscillator. By comparing the force gradients on the corrugated surfaces to that on a smooth, flat surface of the same material, we demonstrate that the Casimir force deviates from the value expected from the pairwise additive approximation and the proximity force approximation. The observed deviation qualitatively agrees with calculations that take into account the interplay between finite conductivity and geometry effects. However, the agreement is not exact, possibly due to uncertainties in the optical properties of the silicon substrate.

A cantilever-based uncooled IR imager was developed utilizing a novel optical readout scheme based on inter-pixel interference. A series of small arrays (approximately 100 × 100 pixels) were fabricated using 8-in. silicon MEMS processes. The array design and process development will be discussed and initial uniformity and imaging results presented. Future challenges in developing a direct-view IR imager will be addressed.

We have fabricated and tested the performance of sub-50nm gate nMOSFETs to assess their suitability for mixed signal applications in the super high frequency (SHF) band, i.e. 3-30GHz. For a 30nm×40 μm×2 device, we found f(T) =465GHz at V(ds)=2V, V(g)=0.67V, which is the highest cut-off frequency reported for a MOSFET produced on bulk silicon substrate so far. However, our measurements of f(max) and noise figure indicate that parasitics impose limitations on SHF operation. We also present a high-frequency ac model appropriate to sub-50nm gate length nanotransistors, which incorporates the effects of the parasitics. The model accurately accounts for measurements of the S and Y parameters in the frequency range from 1 to 50GHz.

An ultra high-density hybrid integration for micro-electromechanical system (MEMS) mirror chips with several thousand inputs/outputs has been developed. The integration scheme involving flip-chip assembly provides electrical signal to individual mirrors, which is compatible with postprocessing steps of selectively removing the silicon handle and releasing the MEMS mirrors. For the first time, to our knowledge, solder deposition and flip-chip bonding of 3-mum bumps on 5-mum centers of a large array has been demonstrated.

We present arrays of electrostatically actuated piston-tip-tilt micromirrors realized using a surface micromachining 3-structural-layer polysilicon process. High fill factor, flat mirrors 120@mm in size have mechanical response in the order of 10@ms, with +/-4^o mechanical tip and tilt and 5@mm piston continuous, controllable range under 110V. The actuator design is based on four dual in-plane comb drives with 0.5@mm critical feature size and high aspect ratio. We show a modular approach to fabricate these arrays, allowing multiple array sizes (64^2 and 256^2 mirrors) and four different designs to be implemented in three DUV masks per lithography level.

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace or (2) arrays of incandescent lamps. Method I was found to yield reduced temperature variability, attributable to smaller temperature differences between the wafer and heat source. The temperature was determined by monitoring test processes involving either the device side or the reverse side of the wafer. These include electrical activiation of implanted dopants after rapid thermal annealing (RTA) or growth of oxide films by rapid thermal oxidation (RTO). Temperature variation data are compared with a model of radiant heating of patterned wafers in RTP systems.

Alternating phase shift technology has been shown to substantially improve focus latitude and resolution for several years. However, the use of phase shift masks to improve the process latitude in gate level lithography has been hindered by the lack of commercially available tools that can convert conventional gate layouts into phase shift mask patterns. A software package has recently become available that allows a user to create phase shift masks to reduce the gate length of features in existing circuit layouts. A digital signal processing chip with 2 million gates has been used as a test vehicle to evaluate the feasibility of phase shifting and processing a large number of devices in a complete circuit. Three wafer lots have been processed with a target feature size of 120 nm with a variation of 25 nm 3σ. The timing circuits of the chips have been tested; those with 120 nm gates showed a nearly fourfold improvement in speed when compared to 240 nm gate circuits at 1 volt operation.

We discuss the fabrication of a FLASH EEPROM floating gate memory device with a cell size of 0.0896@mm. The floating gate level utilized an alternating aperture phase shift mask, a binary mask was used to expose the control gate level. Linewidth changes over topography, due to reflectivity variations, was controlled by an inorganic multilayer anti-reflective coating^1. All levels were exposed with a new generation of photoresists developed at Bell Laboratories with ARCH chemicals. Experiments were carried out to give some insight to the behavior of the materials and the viability of optical enhancement techniques. We have found that 193nm lithography with this new family of photoresists is reasonably proficient in the fabrication of devices with design rules of less than half the exposure wavelength.

To demonstrate the effectiveness of alternating aperture phase shift lithography and 193nm wavelength lithography for integrated circuit technology, two demonstration devices were designed and processed. In one case, a 2 million transistor integrated circuit was processed with phase shifting and 248nm wavelength lithography. Gate lengths were reduced from 240 to 120nm, resulting in a 100MHz circuit speed at 1.0 volt operation, a threefold improvement. In the second case an 80nm floating gate memory device was fabricated with phase shifting, 193nm wavelength lithography, and anti-reflection control. The lithographic results were confirmed by careful measurements throughout the process sequences and finally by the performance of the devices themselves.

In this paper, we tailor the evanescent field coupling between two metal layers with subwavelength slit arrays and created a half-wave plate that imparts a half-wave phase delay to one component of linear polarization. The polarization of linearly polarized light at 1.55 μm wavelength can be rotated by up to 90 degrees, with polarization extinction ratio exceeding 22 dB. One advantage of this device over conventional polarization rotators is that the wavelength of operation can be chosen by fabricating subwavelength slit arrays with different parameters. Moreover, future devices can be designed to be mechanically tunable by suspending one of the metal plates. Nanomechanical motion between the two metal layers changes the evanescent field coupling between them, allowing real time control of the polarization of the transmitted light.

International audience; We measure the Casimir force between a gold sphere and a silicon plate with nanoscale, rectangular corrugations with depth comparable to the separation between the surfaces. In the proximity force approximation (PFA), both the top and bottom surfaces of the corrugations contribute to the force, leading to a distance dependence that is distinct from a flat surface. The measured Casimir force is found to deviate from the PFA by up to 15%, in good agreement with calculations based on scattering theory that includes both geometry effects and the optical properties of the material.

Soft-x-ray projection imaging is demonstrated by the use of 14-nm radiation from a laser plasma source and a single-surface multilayer-coated ellipsoidal condenser. Aberrations in the condenser and the Schwarzschild imaging objective are characterized and correlated with imaging performance. A new Schwarzschild housing, designed for improved alignment stability, is described.

We measure the transmission of IR radiation through double-layer metal films with periodic arrays of subwavelength holes. When the two metal films are placed in sufficiently close proximity, two types of transmission resonances emerge. For the surface plasmon mode, the electromagnetic field is concentrated on the outer surface of the entire metallic layer stack. In contrast, for the guided mode, the field is confined to the gap between the two metal layers. Our measurements indicate that, as the two layers are laterally shifted from perfect alignment, the peak transmission frequency of the guided mode decreases significantly, while that of the surface plasmon mode remains largely unchanged, in agreement with numerical calculations.

A nanopore is an analytical tool with single molecule sensitivity. For detection, a nanopore relies on the electrical signal that develops when a molecule translocates through it. However, the detection sensitivity can be adversely affected by noise and the frequency response. Here, we report measurements of the frequency and noise performance of nanopores

It has been shown that it is possible to produce near diffraction limited images with soft x rays of wavelength 13.8 nm using normal incidence Si/Mo‐multilayered coated optics. Initial experiments with a 20X reduction Schwarzschild optic produced features as small as 50 nm. It is considered that soft x‐ray projection lithography may be a likely candidate for the future generation of lithographic tools needed to produce 0.1‐μm features for integrated circuits around the turn of the century.

Projection imaging of 0.1-microm lines and spaces is demonstrated with a Mo/Si multilayer coated Schwarzschild objective and 14-nm illumination from a laser plasma source. This structure has been etched into a silicon wafer by using a trilevel resist and reactive ion etching. Low-contrast modulation at 0.05-microm lines and spaces is observed in polymethylmethacrylate.

We have demonstrated soft x-ray projection lithography using radiation at wavelengths of 14 nm and 37 nm with a commercially available 20X reduction Schwarzschild camera. Line widths as small as 0.05 microns have been printed. The resolution obtained was essentially diffraction limited. Iridium coated mirrors were used with 37 nm radiation and Mo/Si multilayer coated mirrors with 14 nm radiation. A 1:1 magnification Offner Ring-field system with iridium coated mirrors has been used with 42 nm radiation. This optic has imaged line widths as small as 0.2 microns, which is close to the diffraction limit for this system. Transmission masks were used for all these experiments and the radiation was obtained from an undulator in the Vacuum Ultraviolet Synchrotron Storage Ring at Brookhaven National Laboratory.

We report measurements of the Casimir force between a gold sphere and a silicon surface with an array of nanoscale, rectangular corrugations using a micromechanical torsional oscillator. At distance between 150 nm and 500 nm, the measured force shows significant deviations from the pairwise additive formulism, demonstrating the strong dependence of the Casimir force on the shape of the interacting bodies. The observed deviation, however, is smaller than the calculated values for perfectly conducting surfaces, possibly due to the interplay between finite conductivity and geometry effects., Comment: 5 pages, 3 figures

We review the fabrication process of a recently introduced phase only MEMS based spatial light modulators for maskless lithography. A brief description of this device is presented. The physical properties of its structural layers and the difficulties encountered during its fabrication process are described in detail.

We have fabricated and tested sub-50nm gate length nMOSFETs with fT up to 290GHz to assess their suitability for mixed signal applications in the super high frequency (SHF) band, i.e. 3-30GHz. We have also developed an accurate, high frequency (1 -50GHz) model suitable for integration with digital CMOS

We are exploring the feasibility of sequencing a single molecule of DNA using a revolutionary type of silicon integrated circuit that incorporates an on-chip nanopore mechanism with a molecular trap. The essential component is a single, nanometer-diameter pore in a robust, nanometer-thick membrane formed from a Metal Oxide Semiconductor (MOS) capacitor. To sequence the molecule, the voltage induced by the dipole moment associated with each base is measured using the electrodes on the capacitor as the DNA translocates through the pore.

We describe the design, fabrication and dynamics of a two dimensional array of MEMS piston mirrors that fulfil the requirements needed to modulate deep ultraviolet radiation for mask pattern generation

Membrane deformable mirror devices consist of a single large membrane that is suspended above an array of actuating electrodes. A transparent electrode is incorporated into the membrane mirror device in the optical path in an effort to provide significantly greater control of the membrane, and hence improved performance in an adaptive optics system. The devices presented here were fabricated from 1 mm thickness SOI; devices were bonded to electrode arrays with 1024 electrodes, packaged in ceramic pin grid arrays and driven by off chip D/A electronics. The transparent electrodes consist of glass that is ITO coated for electrical conductivity and visible light transmission. An electrode is inserted into a recessed cavity of each membrane chip, and is positioned 70 mm above the membrane. With 2x2 binned electrodes, the device demonstrates 10 mm deflection toward the electrode array at 40 V. Large deflection at low voltage is obtained because of the low intrinsic stress of the silicon membrane. These data also demonstrate modest deflection toward the transparent electrode, which may be improved with better alignment of the transparent electrode with the underlying membrane and electrode array in future devices.

We describe a prospective strategy for reading the encyclopedic information encoded in the genome: using a nanopore in a membrane formed from a metal-oxide semiconductor (MOS)-capacitor to sense the charge in deoxyribonucleic acid (DNA). In principle, as DNA permeates the capacitor-membrane through the pore, the electrostatic charge distribution characteristic of the molecule should polarize the capacitor and induce a voltage on the electrodes that can be measured. Silicon nanofabrication and molecular dynamic simulations with atomic detail are technological linchpins in the development of this detector. The sub-nanometer precision available through silicon nanotechnology facilitates the fabrication of the detector, and molecular dynamics provides us with a means to design it and analyze the experimental outcomes.

Low stress membrane mirrors will allow improved wave front correction in vision science and astronomical adaptive optics systems. We have fabricated low stress membrane mirrors from single crystal silicon, and flip chip bonded membranes to electrode arrays. These devices operate at lower voltage and have greater stroke than existing membrane mirror devices; they have 256 control electrodes, and are driven by off chip electronics. Devices have a single electrode plane and are pre-biased to allow full wave front correction. We have demonstrated these devices in an adaptive optics system consisting of a coherent source, and a Shack-Hartmann wave front sensor. We compare the experimental performance of the devices to computer simulations and theoretical calculations.

We report the experimental results of the first MOSFET's ever fabricated using a laser plasma-source X-ray stepper. The minimum gate length of these transistors is 0.12 /spl mu/m with an effective channel length of 0.075 /spl mu/m. These transistors were patterned using a mix-and-match lithography scheme where the gate level was printed using a 1.4 nm plasma-source X-ray stepper while the other layers were patterned using optical lithography. >

As telecom networks increase in complexity there is a need for systems capable of manage numerous optical signals. Many of the channel-manipulation functions can be done more effectively in the optical domain. MEMS devices are especially well suited for this functions since they can offer large number of degrees of freedom in a limited space, thus providing high levels of optical integration. We have designed, fabricated and tested optical MEMS devices at the core of Optical Cross Connects, WDM spectrum equalizers and Optical Add-Drop multiplexors based on different fabrication technologies such as polySi surface micromachining, single crystal SOI and combination of both. We show specific examples of these devices, discussing design trade-offs, fabrication requirements and optical performance in each case.

We have achieved extremely high drive current performance and ballistic (T>0.8) transport using ultra-thin (

We are developing membrane mirrors for use in adaptive optics, particularly in astronomy and vision science. We have micro-fabricated membrane mirrors from single crystal silicon using wet chemical etching and reactive ion etching. Membrane size, tension and operating voltage were selected to allow greater deformation of the mirror surface at low operating voltage than previous membrane mirror designs. Mirror devices consist of independently fabricated membrane and electrode array chips that are flip chip bonded together. We have fabricated electrode arrays with 256 and 1024 electrodes, and active diameters ranging from 6-10 mm (comparable to the size of the human pupil). Membrane-electrode hybrids are mounted to ceramic packages, wire bonded, and driven by off chip, D/A electronics. These devices are milestones in the development of an electret membrane mirror.

The design and implementation of 0.15- mu m-channel N-MOSFETs with very high current drive and good short channel behavior at room temperature are discussed. Measured subthreshold characteristics show a slope of 84 mV/dec and a shift for 75 mV for Delta V/sub ds/=1 V. A peak g/sub m/ of 570 mS/mm was recorded, leading to a unity-current-gain cutoff frequency (f/sub T/) of 89 GHz. Key process steps include the formation of 40-AA gate oxides and sub-500-AA junctions. Vertical doping engineering was used to minimize doping at the surface and beneath the junctions, while maintaining good turn-off characteristics. >

We report on fabricated capacitors following B and BF/sub 2/ implantation with near-identical boron profiles as measured by SIMS. The C-V curves showed flatband shifts between the two implanted species which increase with the implant dose, up to 0.27 V for 1e14 cm/sup -2/. Modeling the processing with an interface trap model for boron in the case of BF/sub 2/ implant but not for B, gave good agreement with both SIMS doping profiles and the C-V curves, and reproduced the C-V shifts. This effect is predicted to have a significant impact on MOS V/sub th/.

Summary form only given. We have demonstrated that the threshold voltage shifts in closely spaced, dual-poly CMOS devices are virtually eliminated by using buried, low energy gate implants. The reduced thermal budget for gate activation, made possible by short diffusion distances, not only reduces dopant lateral diffusion in the gates but also in the device channel regions. Moreover, the process allows the use of thinner gate oxides and shallower junctions and improves the control of L/sub eff/.

A 0.25 /spl mu/m coded feature CMOS technology has been developed for high-performance, low-power ASIC applications. Critical process features include 248 nm DUV lithography on all levels, profiled twin tubs by high energy implantation (HEI), dual TiN/polysilicon gates with low resistance on minimum size lines, rapid thermal (RT) N/sub 2/O grown 5.5 nm gate dielectrics, and planarized multi-level interconnect. Transistors are demonstrated with symmetric thresholds and excellent short-channel characteristics down to channel lengths of 0.18 /spl mu/m. Fabricated circuits operate down to

A 1296-port MEMS transparent optical crossconnect with 5.1dB/spl plusmn/1.1dB insertion loss at 1550 nm is reported. Measured worst-case optical crosstalk in a fabric was n38 dB and nominal switching rise/fall times were 5 ms. A 2.07 petabit/s switch capacity was verified upon cross-connecting a forty-channel by 40 Gb/s DWDM data stream through a prototype fabric.

We present the first p-channel Vertical Replacement-Gate (VRG) MOSFETs. Like the VRG-nMOSFETs demonstrated last year, these devices show promise as a successor to planar MOSFETs for highly-scaled ULSI. Our pMOSFETs retain the key features of the nMOSFETs and add channel doping by ion implantation and raised source/drain extensions (SDEs). We have significantly improved the core VRG process to provide high-performance devices with gate lengths of 100 nm and below. Since both sides of the device pillar drive in parallel, the drive current per /spl mu/m of coded width can far exceed that of planar MOSFETs. Our 100 nm VRG-pMOSFETs with t/sub ox/=25 /spl Aring/ drive 615 /spl mu/A//spl mu/m at 1.5 V with I/sub OFF/=8 nA//spl mu/m-80% more drive than specified in the 1999 ITRS Roadmap at the same I/sub OFF/. We demonstrate 50 nm VRG-pMOSFETs with t/sub ox/=25 /spl Aring/ that approach the 1.0 V roadmap target of I/sub ON/=350 /spl mu/A//spl mu/m at I/sub OFF/=20 nA//spl mu/m without the need for a hyperthin (

We present the SALVO CMOS process, first device data and simulation study with the following features: (1) self-aligned local channel implants for SCE reduction; (2) sub-50 nm fabrication using only current production tools; (3) replacement gate with dual-polysilicon for low V/sub T/; (4) low aspect-ratio gates with CD insensitive to lithography and etch profile variability. The first demonstration of SALVO process shows it is a viable candidate for future ULSI CMOS production, in view of its versatility, controllability and compatibility.

We have integrated HfO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics grown by atomic layer chemical vapor deposition (ALD) with poly-Si gate electrodes in the vertical replacement-gate (VRG) MOSFET geometry. These transistors are among the first reported with ALD HfO/sub 2/ gate dielectrics, and have HfO/sub 2/ target equivalent oxide thicknesses (tEOT's) down to 13 /spl Aring/. The poly-crystalline HfO/sub 2/ films in these VRG nMOSFETs exhibit extremely low gate leakage (GL) current densities of J/sub G/ /spl sim/ 10/sup -7/ A/cm/sup 2/ at V/sub G/-V/sub T,Long/ = 0.6 V for 15 /spl Aring/ tEOT devices. This indicates that amorphous gate dielectrics may not be necessary to meet GL requirements. HfO/sub 2/ devices with 50 nm gate length L/sub G/ exhibit drive currents [normalized by the coded width W/sub C/] of 490 /spl mu/A//spl mu/m for 1 V operation (overdrive V/sub GS/-V/sub T/ = 0.6 V) with good short-channel performance. These results demonstrate that ALD is compatible with the demanding VRG geometry, thereby illustrating that it should be well-suited to essentially any novel device structure built with Si-compatible materials.

A projection optical system with 20:1 reduction has been used with radiation at ∼36 nm to evaluate resists for use in soft‐x‐ray projection lithography. The high absorption of soft x rays by carbon‐based polymers requires that an imaging resist layer be very thin. The sensitivities and contrasts of several such resists are reported. By incorporating a thin imaging layer into a trilayer resist scheme, we have exposed, developed, and transferred features as small as 0.2 μm into silicon.

As transistor features shrink into the deep submicron range, a corresponding reduction in the optical wavelength used to pattern such features has also continued. Currently, advanced optical steppers found in ULSI production applications operate at a wavelength of 365 nm with 248 nm optical lithography present in process development facilities and 193 nm lithography in the early stages of research. By reducing the wavelength still further to below 1.5 nm, x-ray lithography represents the ultimate limit of this paradigm. In this paper we present the experimental results of the first MOSFETs ever fabricated using a laser plasma-source x-ray stepper. These transistors were patterned using a mix-and-match lithography scheme where the gate level was printed using a 1.4 nm plasma-source x-ray stepper while the other layers were patterned using an optical stepper operating at a wavelength of 248 nm (DUV). The minimum gate length of these transistors is 0.12 micrometers with an effective channel length of 75 nm.

In order to better understand the mechanics of metallization structures having very fine features, we performed in-situ, temperature-dependent X-ray strain measurements on Al-Cu films patterned into gratings with linewidths of 0.2-0.8μm, with and without a dielectric covering In comparison with earlier work on coarser structures, we find larger strains and less hysteresis, indicating an increased yield stress. The stress in unpassivated lines is almost independent of the linewidth. The slope of the stress/temperature curves for passivated lines increases with decreasing linewidth, so that the compressive stress at 500°C reaches 900MPa for the narrowest lines. The tensile stress at RT is smaller for the narrower lines, suggesting that these lines may not stress-void as much as wider ones. The significance of these results for stress voiding and electromigration will be discussed.

We demonstrate a half wave plate whose principle of operation is based on the strong evanescent field coupling between two metal layers with arrays of subwavelength slits. The device is divided into two kinds of pixels in which the slits are oriented in orthogonal directions. By tuning the phase delay of the transmitted light through the lateral displacement between the top and bottom layers, the polarization of linearly polarized light at 1.55 μm can be rotated by up to 90°. The polarization extinction ratio of the transmitted light exceeds 22 dB.

The feasibility of using X-ray projection cameras as a practical lithography tool for making integrated circuits with tenth-micron features was investigated in experiments performed with a 20-fold reduction Schwarzschild camera operating at 36 nm and 14 nm, and with a 1:1 magnification Offner ring field system at 40 nm. The paper examines the requirements on the resist, the source, the camera design and the fabrication of its mirrors, the mask, and the alignment system. The experiments proved that high-reflectance multilayer mirrors are capable of diffraction limited imaging. Some problems exposed by the experiments, such as the deposition of carbon on surfaces exposed to X-rays, are discussed.

Soft x-ray projection lithography in the 60-400 A wavelength range has recently demonstrated the ability to print 0.1 im resolution features in thin single layer and thicker trilayer resist films.7'8 However, for use on topographic substrates thicker resist layers with planarizing properties probably will be required. This paper analyzes resist absorption and planarization aspects of soft x-ray projection lithography, couples them with projections of potential multilayer and other types of reflectors and reviews resist approaches which are compatible with them. Primarily due to absorption issues and the strong processing tendency to retain a single layer resist technology, dry-developed resist schemes incorporating planarization are favored. Results for a variety of such schemes developed for deep-UV use are surveyed and recent results for soft x-ray exposure at 140 A are discussed.

We demonstrate that the phase of light transmitted through double-layer subwavelength metallic slit arrays can be controlled through lateral shift of the two layers. Our samples consist of two aluminum layers, each of which contains an array of subwavelength slits. The two layers are placed in sufficient proximity to allow coupling of the evanescent fields at resonance. By changing the lateral shift between the layers from zero to half the period, the phase of the transmitted electromagnetic field is increased by pi, while the transmitted intensity remains high. Such a controllable phase delay could open new capabilities for nanophotonic devices that cannot be achieved with single-layer structures.

Spatial light modulators (SLMs) designed to replace photomasks for optical lithography have been designed, fabricated, and tested. These microelectromechanical devices are fabricated with alternating polycrystalline Si and sacrificial SiO2 layers that are patterned by a 193nm wavelength scanner to dimensions as small as 150nm. Aerial image simulations were used to define the mechanical requirements of the devices. Piston motion of electrically actuated devices was measured with an optical profilometer. The measurements were fit to a simple equation to within 1nm precision, which is adequate for defining 50nm features lithographically. Transient response measurements show that one version of the SLM responds to actuation as quickly as 20μs, fast enough for current 193nm wavelength excimer laser sources.