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1. Monolithic TCAD Simulation of Phase-Change Memory (PCM/PRAM) + Ovonic Threshold Switch (OTS) Selector Device

2. Monolithic TCAD simulation of phase-change memory (PCM/PRAM) + Ovonic Threshold Switch (OTS) selector device

4. Process Integration of High Aspect Ratio Vias with a Comparison between Co and Ru Metallizations

8. Supervia Process Integration and Reliability Compared to Stacked Vias Using Barrierless Ruthenium

10. Co Active Electrode Enhances CBRAM Performance and Scaling Potential

11. Three-Layer BEOL Process Integration with Supervia and Self-Aligned-Block Options for the 3 nm Node

13. Atomistic investigation of the electronic structure, thermal properties and conduction defects in Ge-rich GexSe1−x materials for selector applications

14. Thermally stable integrated Se-based OTS selectors with >20 MA/cm2 current drive, >3.103 half-bias nonlinearity, tunable threshold voltage and excellent endurance

15. Compositional depth profiling of TaCN thin films

16. Highly reliable TaOx ReRAM with centralized filament for 28-nm embedded application

18. Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

20. Thermal and Plasma Treatments for Improved (Sub-)1nm EOT Planar and FinFET-based RMG High-k Last Devices and Enabling a Simplified Scalable CMOS Integration Scheme

21. The Effects of Plasma Treatments and Subsequent Atomic Layer Deposition on the Pore Structure of a k = 2.0 Low-k Material

23. Impact of H-2/N-2 annealing on interface defect densities in Si(100)/SiO2/HfO2/TiN gate stacks

24. W vs. Co-Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22nm Tech. Nodes

25. Effective Work Function Engineering for Aggressively Scaled Planar and FinFET-based Devices with High-k Last Replacement Metal Gate Tech.

27. Scalability of plasma enhanced atomic layer deposited ruthenium films for interconnect applications

29. Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

30. Scaling of high-k dielectrics towards sub-Inm EOT

31. Key sub 1nm EOT CMOS enabler by comprehensive PMOS design

32. Interface stability in advanced high-κ-metal-gate stacks

34. Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

35. Low VT metal-gate/high-k nMOSFETs — PBTI dependence and VT Tune-ability on La/Dy-capping layer locations and Laser annealing conditions

36. Low VT CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

37. Nitrogen Profile and Dielectric Cap Layer (Al2O3, Dy2O3, La2O3) Engineering on Hf-Silicate

38. A Dy2O3-capped HfO2 Dielectric and TaCx-based Metals Enabling Low-Vt Single-Metal-Single-Dielectric Gate Stack

39. Aqueous Chemical Solution Deposition

41. Metallorganic Chemical Vapor Deposition of Dysprosium Scandate High-k Layers Using mmp-Type Precursors

42. Ternary rare-earth metal oxide high-k layers on silicon oxide

46. Implementation of high-k gate dielectrics - a status update

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