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As antenna element size and pitch are in the order of millimeters, i.e. comparable to wavelength at millimeter‐wave (mmWave) frequencies, antenna‐in‐package (AiP) solutions are more feasible for design and manufacturing than at other frequencies. This chapter first discusses the needs and challenges of performing electrical, mechanical, and thermal co‐design for AiP modules with a particular focus on mmWave front‐end module implementation in 28‐GHz high‐speed wireless data transmission applications. Furthermore, it reviews the thermal management considerations for next‐generation heterogeneous integrated systems that are also applicable to phased array front‐end modules. Different cooling methodologies are discussed for future communication devices under various power dissipation conditions. During the design iterations, simulation and measurement of key aspects such as antenna performance (bandwidth, gain, radiation patterns), cooling solutions, and warpage conditions need to be evaluated and optimized to ensure that performance meets the overall system specifications.

The increasing capabilities of high‐speed silicon technologies have made millimeter‐wave frequencies attractive for low‐cost applications. This chapter focuses on large‐array antenna‐in‐package (AiP) designs based on surface laminar circuit (SLC) technology at 28 and 94 GHz. It investigates antenna designs considering both manufacturability and the general performance requirements and presents a 30.5‐GHz antenna design and associated characterization results. The antenna design is based on SLC technology and supports both horizontal and vertical polarizations to enable realization of a large phased‐array module with multiple simultaneous beams for 5G applications. The chapter provides information on the AiP portion of the first reported SiGe‐based scalable phased‐array module to illustrate the challenges and initial solutions. Millimeter‐wave scaled phased arrays support many antenna elements. Phased‐array scaling is advantageous because it provides a path for supporting antenna arrays with a larger number of elements than a single integrated circuit can support.

Silicon-based millimeter-wave (mm-wave) phased-array technologies are enabling directional wireless data communications at Gb/s speeds. In this paper, we review and discuss the challenges of implementing a multichip phased-array antenna module for mm-wave applications using organic buildup substrate technology. A prototype test vehicle has been fabricated and studied to evaluate the antenna and interconnect performance, dielectric properties, package substrate warpage conditions at different temperatures, chip- and board-level joint process reliability, and thermal management feasibility for cooling. Based on the learning from the test vehicle, an organic-based multilayered phased-array antenna package for 28-GHz mm-wave radio access applications is implemented. The package incorporates 64 dual-polarized antenna elements and features an air cavity common to all antennas. Direct probing measurements on a single-antenna element of the package show over 3 GHz of bandwidth and 3-dBi gain at 28 GHz. A phased-array transceiver module has been developed with the package; the module includes four SiGe BiCMOS ICs attached using flip-chip assembly. Module-level measurements in the TX mode show a 35-dB near-ideal output power increase for 64-element power combining; 64-element radiation pattern measurements are reported with a steering range of ± 50° without tapering in off-boresight directions, and 64-element radiation pattern measurements with tapering show achievement of a sidelobe level lower than −20 dB. The transceiver modules achieved 20.64-Gb/s throughput with 256 QAM and 800-MHz bandwidth in direct over-the-air link measurement results.

This paper reports the development of a compact and highly programmable 28-GHz phased array subsystem that is currently being integrated in a city-scale testbed for advanced wireless research and experimentation. The subsystem hardware consists of a 28-GHz 64-element state-of-the-art dual-polarized phased array antenna module (PAAM), low-noise DC-DC power regulators with a single 12-V input, current sensors and an ADC for real-time supply monitoring, a PLL for LO (5 GHz) generation, IF (3 GHz)/LO splitters, IF/LO baluns, and programmable switches. All of these components are integrated in a compact (10” x5.75”) PCB which also supports the direct plug-in of a commercial-off-the-shelf FPGA system-on-module (SoM). The IF switches and splitters couple the PAAM to 20 IF ports that enable a rich set of MIMO configurations, including up to 8 simultaneous 16-element independent beams in each TX/RX mode. The FPGA and associated software enable the configuration of all subsystem features from a high-level application program interface (API), facilitating MIMO millimeter-wave wireless experiments. 28-GHz channel sounding measurements using the phased array subsystem coupled with software-defined radios is presented as a testbed-level experiment example.

This paper presents novel antenna designs and integration methods that enable a low-cost scalable antenna-in-package (AiP) phased-array solution for wideband wireless communication covering 24 GHz - 30 GHz (N257, N258 and N261 5G bands). A total number of 26 dual-polarized antenna variants based on two implementation approaches were fabricated on a $\mathrm{47.5}\text{mm}\times \mathrm{47.5}\text{mm}$ package test vehicle with an element-to-element pitch of 5.9 mm. The first approach consists of integrating a magneto-electric dipole antenna array in a single laminate and the second approach consists of an aperture-coupled patch antenna array implemented in a superstrate forming a 2-laminate structure. Passive measurement results demonstrate the feasibility of achieving more than 5GHz input return loss bandwidth and 7dBi peak antenna gain with over 20dB cross-polarization isolation at 28 GHz, as well as near-identical radiation patterns for both H and V polarizations. In addition, the AiP test vehicle contains two $\mathrm{4}\times \mathrm{4}$ antenna arrays (one for each design approach) that support integration with 28-GHz SiGe phased array RFICs for active testing. Over-the-air active module measurement results are reported, including near-ideal spatial power combining, antenna gain uniformity across elements within +/-2.5dB, as well as 16-element beam-forming and beam-steering in a ±60° range.

In this article, we present a low-power, small form-factor, 60-GHz packaged radio featuring broad beam coverage. We increase angular coverage by beam switching between two orthogonally pointed low directivity beams that are created using two different antennas integrated in package. The resulting wide angular coverage of the radio makes radio links robust to movement and rotation; this improvement overcomes a key challenge for millimeter-wave (mmWave) deployment in portable electronics. We incorporate a 3.2 mm $\times $ 3.2 mm 32-nm CMOS radio integrated circuit (IC) in the package for radio functions. The IC includes TX and RX RF front ends, up- and down-conversion mixers, TX and RX analog baseband circuits, a common PLL, TX and RX LO chains, and ADCs and a micro-controller for built-in self-test (BIST). The IC is flip-chip packaged on a four-layer organic package comprising two TX antennas and two RX antennas. In board-level over-the-air measurements of the half-duplex packaged radio, 17.1-dBm effective isotropic radiated power (EIRP) and 6.1-dB noise figure are achieved in the TX and RX modes respectively, with power consumption below 250 mW in either mode. We characterized the radio over the air using 802.11ad waveforms; the radio is 802.11ad compliant in both TX and RX modes at data rates up to the maximum 802.11ad PHY rate of 4.62 Gb/s (raw data rate >7 Gb/s) with a TX EVM $\pi $ steradians in first-of-a-kind measurements. The radio maintains 802.11ad compliance over 2.9 $\pi $ steradians solid angle.

This paper presents the first reported 28-GHz phased-array IC for 5G communications. Implemented in 130-nm SiGe BiCMOS, the IC includes 32 TRX elements and features concurrent independent beams in two polarizations in either TX or RX operation. Circuit techniques to enable precise beam steering, orthogonal phase and amplitude control at each front end, and independent tapering and beam steering at the array level are presented. A TX/RX switch design is introduced which minimizes TX path loss resulting in 13.5 dBm/16 dBm Op1dB/Psat per front end with >20% peak power added efficiency of the power amplifier (including switch and off-mode LNA) while maintaining a 6 dB noise figure in the low noise amplifier (including switch and off-mode PA). Comprehensive on-wafer measurement results for the IC across multiple samples and temperature variation are presented. A package with four ICs and 64 dual-polarized antennas provides eight 16-element or two 64-element concurrent beams with 1.4°/step beam steering (

Phased-array modules at frequencies >20 GHz are expected to play an important role for 5G applications. Antenna-in-package (AiP) is a reliable and cost-effective method to realize these phased arrays. This paper introduces a practical Ka-band AiP structure and discusses the antenna element design and implementation tradeoffs. The AiP design is based on multilayer organic buildup substrates that are suitable for phased-array module integration needs and supports both horizontal and vertical polarizations. Measurement results from the fabricated antenna prototypes show 0.8 GHz return loss bandwidth and 3.8-dBi peak gain at 30.5 GHz. Simulation results agree with the measured ones.

This paper presents an aperture-coupled dual-polarized stacked patch antenna integrated in an RFIC package environment for Ka-band applications. The package is based on multilayer organic technology, so it can be fabricated by PCB manufacturers. The antenna has a measured peak gain > 5 dBi and supports a 4 GHz bandwidth.

Compact phased array transmitter (TX) and receiver (RX) modules operating at 94 GHz are presented and demonstrated in a 3D radar imaging system. Each module consists of four SiGe ICs and a package that integrates 8X8 dual-polarized antennas and 10-GHz IF power combiners. Each TX and RX IC integrates beam-forming, frequency conversion, LO generation, and digital control functions. The modules have beam steering capabilities in both azimuth and elevation over a range of +/- 32 degrees. A radar imaging system is implemented comprising an evaluation board with one TX module and one RX module, FMCW signal generation and acquisition components, and an FPGA for fast beam steering control. The system can steer TX and RX beams to a given direction and perform a radar measurement in that direction in less than 100us, enabling 3D imaging in real time. Measurement results are presented for the modules and the prototype imaging system.

To address the abating performance improvements from device scaling, innovative 2.5-D and 3-D integrated circuits with vertical interconnects called through-silicon vias (TSVs) have been widely explored. This paper reviews TSVs with focus on the following: 1) key drivers for TSV-based integration; 2) TSV fabrication techniques; 3) TSV electrical and thermomechanical performance fundamentals and characterization techniques; and 4) novel technologies to attain enhanced performance beyond the state-of-the-art TSVs.

We report on efforts to develop a high speed, low cost, low energy chip scale optical module for co-packaging on a first-level organic substrate for HPC and Data Center applications.

The paper introduces a software-defined phased array radio (SDPAR) operating around the 5G NR frequency band of 28 GHz. The highly re-configurable phased array radio features beam shaping/steering control as well as data TX/RX function control from a single Python-based software interface. High speed phased array control and configuration functions are enabled by extensive on-chip digital circuits co-integrated with mmWave circuit blocks to achieve agile beam-steering and beam-shaping functions. Beams are formed using up to 128 independently controlled phased array elements using RF beamforming for groups of 16 elements, and IF/digital beamforming thereafter. Both TX and RX capabilities are enabled in both H and V polarizations. These functions are accessed through a software stack providing a top level application programming interface (API) for user programmability. The same API also controls the data communication functions with both TX and RX capabilities enabling USRP-GNU radio functions at around 28 GHz frequency. In addition to the hardware platform, this paper presents a software-only SDPAR emulator to enable fast software-only development cycles prior to real-world experiments using the SDPAR hardware. The SDPAR system platform is expected to significantly benefit networking research for mmWave phased array systems, especially targeted toward 5G communications.

An organic-based multi-layered phased-array antenna package for 94-GHz radar imaging and communication applications is hereby introduced. The package incorporates 64 dual-polarized antenna elements. Direct antenna probing measurements on a fabricated package and full-wave electromagnetic (EM) simulation of the complete design show over 8 GHz bandwidth and 2 dBi gain at 94 GHz. 64-element beam forming and beam steering are evaluated through EM simulations showing 12-degree half-power beam width and lower than -20dB side levels. A novel flip-chip assembly process is introduced to improve module-level yield and scalability by attaching the package with one die that consists of four joint ICs.

Co-design and integration of RFIC, package, and antennas are critical to enable 5G wireless communications and is particularly challenging at mmWave frequencies. This paper reviews two different aspects of mmWave antenna module packaging and integration for base station and user equipment applications, respectively. We first present the challenges, implementation, and characterization of a 28­GHz phased-array module with 64 dual polarized antennas for 5G base station applications. Next, we describe a compact, low-power, 60-GHz switched-beam transceiver module suitable for handset integration incorporating 4 antennas that supports both normal and end-fire directions for a wide link spatial coverage.

Directional communication at millimeter-wave (mmWave) frequencies is one of the key technologies under development towards the anticipated deployment of fifth generation mobile access (5G). Silicon-based multi-antenna systems are strong candidates for the implementation of such directional links; however, the performance requirements are in general significantly more challenging than those posed by mmWave WLAN links demonstrated so far (e.g. for 802.11ad). This work presents an overview of recent innovations in circuit design, antenna design, and beamforming architecture which enable complex phased arrays with precise and agile beamforming for mmWave-based 5G communications. Specifically, this work discusses: (1) a 28-GHz phase shifting transceiver front end, (2) beamforming architecture considerations to enable dual polarized operation as well as multi beam configurability, and (3) two different 28-GHz antenna-in-package (AiP) designs. These advances have been jointly demonstrated in a 64-element dual polarized phased array antenna module (PAAM) consisting of four SiGe ICs and an AiP array. The PAAM supports two simultaneous and independent 64-element beams in either TX or RX modes. PAAM-level measurement results over the air without calibration show +/− 50° beam scanning with >10dB silde-lobe rejection

In a world of digitally native citizens, processors and memory are common topics of conversation, no longer restricted to the engineering community. It is only natural. After all, one does not need to be an architect to appreciate the skyline of a modern metropolis. But behind this postcard image is a complex world of substrates and interconnects and buffers and packages. Smartphones and self-driving vehicles require advanced printed circuit board (PCB) and IC design. Advanced design relies on specialized computer-aided design (CAD) tools. CAD requires modeling and an entire field of mathematical know-how. But technology exists in the physical realm. Progress is also driven by the advance of materials and manufacturing techniques. Prototyping requires accurate measurements and precise characterization. Layers upon layers of knowledge and expertise make the intricate infrastructure of modern electronics possible. We seek to give an overview of the recent innovations across these layers. This special section is built from selected work initially presented at the SPI 2018, EPEPS 2018, and EDAPS 2018, conferences that are co-sponsored by the IEEE Electronics Packaging Society (EPS).

A hybrid 3-D and equivalent 2-D finite-element method (FEM) is proposed for signal/power integrity analysis of multiple vias in a shared anti-pad in an arbitrarily shaped parallel-plate pair. The entire domain of the plate pair is decomposed into via-domains and plate domains by virtual interfaces. Complicated fields in via-domains, due to mode conversions from transverse electromagnetic modes in anti-pads or via-holes to parallel-plate modes, are described by a 3-D FEM while in plate domains, only the zeroth-order parallel-plate modes are assumed to exist a little far away from anti-pads. Triangular prism elements are utilized in both via-domains and plate domains. It is proven that the 3-D triangular prism element can be reduced to an equivalent 2-D triangle element by a novel edge numbering process and the boundary conditions along the interfaces of via-domains and plate domains can be automatically satisfied. The accuracy of the hybrid method has been validated by comparison with other numerical methods, and its flexibility, as well as efficiency, are also demonstrated.

An organic-based multi-layered phased-array antenna package for a 28GHz 5G radio access applications is hereby introduced. The package incorporates 64 dual-polarized antenna elements and features an air cavity common to all antennas. Direct antenna probing measurements of the package show over 3GHz bandwidth and 3dBi gain at 28GHz. A phased array transceiver module has been developed with the package and four SiGe BiCMOS ICs are attached using flip-chip assembly. Module-level measurements in TX mode show 54dBm EIRP and near-ideal 35dB gain increase for 64-element power combining. 64-element radiation pattern measurements are reported with a steering range of > ±40 degrees without tapering in off-boresight direction.

To achieve a target data bandwidth in high-speed channels, an on-board channel modeling study was presented in this paper. A design guideline was found by observing the variation of link performance, depending on parameters such as channel length, baud rate, and the number of signal layers. The channel performance was investigated using a newly developed parametric simulation environment supported by a fast multilayered via transition modeling tool. The extensive parameter sweep simulations showed that an allowable channel reach has a lower and an upper bound limited by stub via effect and trace loss, respectively. Under a specified channel reach, the aggregate data bandwidths were estimated using a particle swarm optimization routine, and a tradeoff relation among the wiring capability and the maximum allowable data rate was observed. From these observations, the approach provides a guideline to select the number of signal layers for achieving the required data bandwidth.

Electrical loss and substrate noise coupling induced by through-silicon-vias (TSVs) in silicon-on-insulator (SOI) substrates is characterized in frequency and time domains. A three-dimensional (3-D) test site in 45-nm CMOS SOI including copper-filled TSVs and microbumps ( μC4's) is fabricated and measured to extract the interconnect loss. Good correlation to the electrical circuit models is demonstrated up to 40 GHz. In addition to a buried oxide layer, a highly doped N+ epilayer used for deep trench devices in 22-nm CMOS SOI is considered in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A noise mitigation technique of using CMOS process compatible buried interface contacts is proposed and studied. Simulation results demonstrate that a low-impedance ground return path can be readily created for effective substrate noise reduction in 3-D IC design.

Next-generation mobile technology (5G) aims to provide an improved experience through higher data-rates, lower latency, and improved link robustness. Millimeter-wave phased arrays offer a path to support multiple users at high data-rates using high-bandwidth directional links between the base station and mobile devices. To realize this vision, a phased-array-based pico-cell must support a large number of precisely controlled beams, yet be compact and power efficient. These system goals have significant mm-wave radio interface implications, including scalability of the RFIC+antenna-array solution, increase in the number of concurrent beams by supporting dual polarization, precise beam steering, and high output power without sacrificing TX power efficiency. Packaged Si-based phased arrays [1–3] with nonconcurrent dual-polarized TX and RX operation [2,3], concurrent dual-polarized RX operation [3] and multi-IC scaling [3,4] have been demonstrated. However, support for concurrent dual-polarized operation in both RX and TX remains unaddressed, and high output power comes at the cost of power consumption, cooling complexity and increased size. The RFIC reported here addresses these challenges. It supports concurrent and independent dual-polarized operation in TX and RX modes, and is compatible with a volume-efficient, scaled, antenna-in-package array. A new TX/RX switch at the shared antenna interface enables high output power without sacrificing TX efficiency, and a t-line-based phase shifter achieves

This paper presents issues and practical solutions for SIW designs with very thin substrate with high profile metal roughness at mmWave frequencies.

A low power, small form-factor, 60-GHz radio with beam switching capability is presented. The 3mm×3mm radio IC in 32nm SOI CMOS includes the TX and RX RF front ends, mixers, basebands, PLL and LO chains. The package comprises 2 TX antennas and 2 RX antennas producing low directivity beams in two orthogonal directions to maximize spatial coverage, with an achieved angular coverage of 254°. In board level measurements of the half duplex packaged radio, 17.1dBm EIRP and 6.1dB noise figure are achieved, with power consumption below 250mW.

This paper explores the electrical performance of a recessed probe launch (RPL) technique for measurement of embedded (internal) printed circuit board (PCB) structures such as striplines and vias (plated through holes). The RPL uses high-frequency microprobes in combination with a milling technique that removes upper board layers and exposes internal probing points. A two-tier calibration technique is applied for the extraction of the S-parameters of the RPLs with the help of thru-reflect-line calibration standards designed on PCB. Full-wave models are used to corroborate and validate the obtained S-parameters. Good model-to-hardware correlation is obtained up to 40 GHz. Furthermore, the launch performance with respect to microprobe positioning and variations of the cavity size is investigated using the full-wave models. These simulations suggest techniques for launch optimization and probe modifications that improve the launch measurement bandwidth.

This paper studies the accuracy of the physics-based via model, specifically when applied to dense via arrays. The physics-based model uses Green's functions for cylindrical waves in radial waveguides to model the via return current paths and the coupling between vias. The effects of approximations made in this model are studied with regard to four types of modes based on an eigenmode expansion for the radial waveguide. It is found that for the mode conversion in the vicinity of the via, an accurate consideration of nonpropagating modes becomes critical with an increasing cavity height. For the interaction between vias in dense arrays, anisotropic modes have an impact for small pitches, whereas the coupling by nonpropagating modes is small for practical printed circuit board dimensions. For a data rate of 20 Gb/s, conclusions with regard to the applicability of the physics-based via model to a multilayer structure are drawn. For 80-mil pitch, a good agreement to full-wave results can be observed. Measurements have been carried out to validate this finding. For 40-mil pitch, the accuracy of the physics-based via model is not sufficient for data rates of 20 Gb/s or higher.

A source synchronous I/O system based on high-density silicon carrier interconnects is introduced. Benefiting from the advantages of advanced silicon packaging technologies, the system uses 50 μm-pitch μC4s to reduce I/O cell size and fine-pitch interconnects on silicon carrier to achieve record-breaking interconnect density. An I/O architecture is introduced with link redundancy such that any link can be taken out of service for periodic recalibration without interrupting data transmission. A timing recovery system using two phase rotators shared across all bits in a receive bus is presented. To demonstrate these concepts, an I/O chipset using this architecture is fabricated in 45 nm SOI CMOS technology. It includes compact DFE-IIR equalization in the receiver, as well as a new all-CMOS phase rotator. The chipset is mounted to a silicon carrier tile via Pb-free SnAg μ C4 solder bumps. Chip-to-chip communication is achieved over ultra-dense interconnects with pitches of between 8 μm and 22 μm. 8 × 10-Gb/s data is received over distances up to 4 cm with a link energy efficiency of 5.3 pJ/bit from 1 V TX and RX power supplies. 8 × 9-Gb/s data is recovered from a 6-cm link with 16.3 dB loss at 4.5 GHz with an efficiency of 6.1 pJ/bit.

This paper presents a design and modeling methodology of vertical interconnects for three-dimensional integration (3DI) applications. Compact semi-analytical wideband circuit level models have been developed based on explicit expressions. The pronounced frequency dependent silicon substrate induced dispersion and loss effects are considered, as well as skin and proximity effects. The models have been verified against numerical computations (full wave HFSS and quasi-static Q3D solvers). A dedicated test site has been designed for broadband characterization (from 1 MHz up to 110 GHz) of TSVs within a dense farm.