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5. Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

Author

Gupta, Anshul, primary, Pedreira, Olalla Varela, additional, Arutchelvan, Goutham, additional, Zahedmanesh, Houman, additional, Devriendt, Katia, additional, Mertens, Hans, additional, Tao, Zheng, additional, Ritzenthaler, Romain, additional, Wang, Shouhua, additional, Radisic, Dunja, additional, Kenis, Karine, additional, Teugels, Lieve, additional, Sebai, Farid, additional, Lorant, Christophe, additional, Jourdan, Nicolas, additional, Chan, Boon Teik, additional, Subramanian, Sujith, additional, Schleicher, Filip, additional, Hopf, Toby, additional, Peter, Antony Premkumar, additional, Rassoul, Nouredine, additional, Debruyn, Haroen, additional, Demonie, Ingrid, additional, Siew, Yong Kong, additional, Chiarella, Thomas, additional, Briggs, Basoene, additional, Zhou, Xiuju, additional, Rosseel, Erik, additional, De Keersgieter, An, additional, Capogreco, Elena, additional, Litta, Eugenio Dentoni, additional, Boccardi, Guillaume, additional, Baudot, Sylvain, additional, Mannaert, Geert, additional, Bontemps, Noemie, additional, Sepulveda, A., additional, Mertens, Sofie, additional, Kim, Min-Soo, additional, Dupuy, Emmanuel, additional, Vandersmissen, Kevin, additional, Paolillo, Sara, additional, Yakimets, Dmitry, additional, Chehab, Bilal, additional, Favia, Paola, additional, Drijbooms, Christel, additional, Cousserier, Joris, additional, Jaysankar, Manoj, additional, Lazzarino, Frederic, additional, Morin, Pierre, additional, Altamirano, Efrain, additional, Mitard, Jerome, additional, Wilson, Christopher J., additional, Holsteyns, Frank, additional, Boemmels, Juergen, additional, Demuynck, Steven, additional, Tokei, Zsolt, additional, and Horiguchi, Naoto, additional

Published
2020
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6. Ge Devices: A Potential Candidate for Sub-5-nm Nodes?

Author

Sharan, Neha, primary, Eneman, Geert, additional, Collaert, Nadine, additional, Parvais, Bertrand, additional, Spessot, Alessio, additional, Mocuta, Anda, additional, Shaik, Khaja A., additional, Jang, Doyoung, additional, Schuddinck, Pieter, additional, Yakimets, Dmitry, additional, Bardon, Marie Garcia, additional, Mitard, Jerome, additional, Arimura, Hiroaki, additional, and Bufler, Fabian M., additional

Published
2019
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8. Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI

Author

Hills, Gage, primary, Bardon, Marie Garcia, additional, Doornbos, Gerben, additional, Yakimets, Dmitry, additional, Schuddinck, Pieter, additional, Baert, Rogier, additional, Jang, Doyoung, additional, Mattii, Luca, additional, Sherazi, Syed Muhammed Yasser, additional, Rodopoulos, Dimitrios, additional, Ritzenthaler, Romain, additional, Lee, Chi-Shuen, additional, Thean, Aaron Voon-Yew, additional, Radu, Iuliana, additional, Spessot, Alessio, additional, Debacker, Peter, additional, Catthoor, Francky, additional, Raghavan, Praveen, additional, Shulaker, Max M., additional, Wong, H.-S. Philip, additional, and Mitra, Subhasish, additional

Published
2018
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10. Vertical Transistors: a Slippery Path towards the Ultimate CMOS Scaling : Verticale Transistors: een glibberig pad naar het uiteindelijke CMOS schalen

Author

Yakimets, Dmitry, Collaert, Nadine, and De Meyer, Kristin

Subjects
Hardware_INTEGRATEDCIRCUITS
Abstract

The semiconductor industry has largely relied on Moore’s law, based on the observation that every new generation of transistors has been better than the previous one in Power, Performance, Area and Cost (PPAC) metrics simultaneously. However, this trend is under a pressure now. The main issue is related to the enormous complexity of both technology and design, which drastically raises not only the manufacturing, but also the R&D costs. Therefore, in order to minimize risks and maximize benefits of a new technology, it is being co-optimized hand in hand with a design relying on this technology. The scaling of lateral transistors is going to reach its limit soon because it mainly relies on the scaling of contacted gate pitch (CGP), which, in turn, forces the scaling of gate length, S/D spacers and contacts. Reduction of any of these dimensions is undesirable as it leads to poorer electrostatic control, increased parasitic capacitance and increased access resistance, respectively. There are lateral devices, like nanowire-based FETs, which may postpone the problem of CGP budgeting but they cannot solve it. The focus of this PhD work is on the vertical devices. These devices are less constrained on gate length and spacer thickness as they are oriented vertically and thus should demonstrate better scalability than lateral transistors. We quantify the advantages of the vertical devices in terms of PPA metrics through a holistic benchmark by combining the design techniques and technology limitations which are likely to be in place at the 5nm technology. In order to do this, we perform the layouts analysis, model and evaluate RC parasitics, calibrate compact models to TCAD and experimental data. Afterwards, we run simulations on a ring oscillator level to extract the PPA metrics. We have not limited ourselves to the conventional MOSFETs only, but we also benchmark vertical III-V heterojunction Tunnel FETs in order to get a better understanding under which conditions the vertical architecture is the most advantageous. This allows us to shed light on the ultimate CMOS scaling and to understand whether the introduction of vertical transistors can enable the next technological nodes. nrpages: 143 status: published

Published
2017

14. (Invited) Vertical Nanowire FET Integration and Device Aspects

Author

Veloso, Anabela, primary, Altamirano-Sánchez, Efraín, additional, Brus, Stephan, additional, Chan, B. T., additional, Cupak, Miroslav, additional, Dehan, Morin, additional, Delvaux, Christie, additional, Devriendt, Katia, additional, Eneman, Geert, additional, Ercken, Monique, additional, Huynh-Bao, Trong, additional, Ivanov, Tsvetan, additional, Matagne, Philippe, additional, Merckling, Clement, additional, Paraschiv, Vasile, additional, Ramesh, Siva, additional, Rosseel, Erik, additional, Rynders, Luc, additional, Sibaja-Hernandez, Arturo, additional, Suhard, Samuel, additional, Tao, Zheng, additional, Vecchio, Emma, additional, Waldron, Niamh, additional, Yakimets, Dmitry, additional, De Meyer, Kristin, additional, Mocuta, Dan, additional, Collaert, Nadine, additional, and Thean, Aaron, additional

Published
2016
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21. Benchmarking of MoS2 FETs With Multigate Si-FET Options for 5 nm and Beyond.

Author

Agarwal, Tarun, Yakimets, Dmitry, Raghavan, Praveen, Radu, Iuliana, Thean, Aaron, Heyns, Marc, and Dehaene, Wim

Subjects
*FIELD-effect transistors, *MOLYBDENUM sulfides, *SILICON, *BILAYERS (Solid state physics), *PERFORMANCE evaluation
Abstract

In this paper, we benchmark the performance of monolayer and bilayer MoS2 FETs (MFETs) against various multigate (MuG) Si-FET options, such as FinFETs and lateral and vertical nanowire FETs, for a 5-nm node and beyond. We compare the performance metrics of all the device options at the ring-oscillator (RO) level, accounting for not only intrinsic and extrinsic parasitic elements but also interconnects. Using the atomistic two-band ballistic quantum transport simulations, we evaluate ON-current and intrinsic capacitances for MoS2-based devices. Furthermore, we calibrate two-band model currents with more sophisticated full-band diffusive simulations to obtain realistic performance metrics at the circuit level. We show that both the intrinsic and parasitic capacitances of a single-gate MFET are lesser than those of a double-gate (DG) MFET, resulting in 13% lesser energy consumption. A DG bilayer (DGBL) MFET shows the best performance among different MFETs. In comparison toMuG FETs, the DGBL MFET offers not only lower energy consumption but also 35%–45% lower speed. In the end, to meet the target performance, we evaluate the impact of the device current, contact resistance, and back-end-of-the-line load on the speed of RO with the DGBL MFET. [ABSTRACT FROM PUBLISHER]

Published
2015
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22. Vertical GAAFETs for the Ultimate CMOS Scaling.

Author

Yakimets, Dmitry, Eneman, Geert, Schuddinck, Pieter, Bao, Trong Huynh, Bardon, Marie Garcia, Raghavan, Praveen, Veloso, Anabela, Collaert, Nadine, Mercha, Abdelkarim, Verkest, Diederik, Thean, Aaron Voon-Yew, and De Meyer, Kristin

Subjects
*FIELD-effect transistors, *INTEGRATED circuit design, *SWITCHING circuits, *ELECTRIC oscillators, *ELECTRODES, DESIGN & construction
Abstract

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules. [ABSTRACT FROM AUTHOR]

Published
2015
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