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Background Left-behind children in China, who live without one or both parents due to migration, are highly susceptible to various physical and mental health issues, including injuries. The promotion of their well-being and the reduction of harm incidences depend on crucial factors such as social support, self-esteem, and resilience. However, the underlying mechanisms for achieving these goals remain unclear. Objective The purpose of this study is to investigate the chain-mediating effects of self-esteem and psychological resilience between perceived social support and the number of injuries experienced in the last year among left-behind children in order to establish a foundation for the development of effective injury prevention strategies. Methods The survey data for this study was collected from 1005 left-behind children in the Chaoshan region, China, between September 2019 and September 2020. The survey included the Juvenile Victimization Questionnaire Revised 2 (JVQ R2), as well as the Rosenberg Self-Esteem Scale, Perceived Social Support Scale, and Psychological Resilience Scale. Chain-Mediating effect was worked out by using AMOS structural equation model (SEM), and the significance of mediation was examined by bootstrap. Results (1) A linear regression analysis showed that perceived social support was positively correlated with self-esteem (r=0.25, PConclusions The findings of this study suggest that social support can reduce the risk of injury of left-behind children in the Chaoshan region, and indirectly reduce the risk of injury of left-behind children through the chain-mediating effect of self-esteem and psychological resilience. Thus, enhancing the perceived social support, self-esteem, and psychological resilience of left-behind children may promote their physical and mental well-being and lower their vulnerability to injuries.

Anxiety disorders are a major public health concern in China. Previous studies have provided evidence for associations between ambient temperature and anxiety outpatient visits, but no studies have examined short-term effects of other meteorological factors such as sunshine duration, wind speed and precipitation on increased anxiety outpatient visits. We aimed to assess the association between climatic factors and outpatient visits for anxiety in Suzhou, a city with a temperate climate in Anhui Province, China. Daily anxiety outpatient visits, meteorological factors, and air pollutants from 2017 to 2019 were collected. A quasi-Poisson generalized linear regression model combined with distributed lag non-linear model (DLNM) was used to quantify the effects of extreme meteorological factors (sunshine duration, wind speed and precipitation) on anxiety outpatient visits. All effects were presented as relative risk (RR), with the 90th and 10th percentiles of meteorological factors compared to the median. Subgroup analyses by age and gender were performed to identify susceptible subgroups. A total of 11 323 anxiety outpatient visits were reported. Extremely low sunshine duration, low and high speed speed increased the risk of anxiety outpatient visits. The strongest cumulative effects occurred at lag 0–14 days, and the corresponding RRs of extremely low sunshine duration, low and high wind speed were 1.417 (95% CI: 1.056–1.901), 1.529 (95% CI: 1.028–2.275) and 1.396 (95% CI: 1.007–1.935), respectively. Subgroup analyses showed that males and people aged ≥ 45 years appeared to be more susceptible to the cumulative effects of extremely low sunshine duration. In addition, the adverse effects of extreme wind speed were more pronounced in the cold season. This study provides evidence that extreme climatic factors have a lagged effect on anxious outpatient visits. In the context of climate change, these findings may help develop weather-based early warning systems to minimize the effects of extreme meteorological factors on anxiety.

As AI applications become pervasive on edge device, incrementally learning new tasks is demanded for deep neural network (DNN) models. In this article, we proposed AILC, a compute-in-memory (CIM)-based accelerator for on-chip incremental learning using STT-MRAM technology. On the software side, a network-expansion-based low-precision training algorithm is proposed for incremental learning, where the loss function is modified to handle the unbalanced training dataset. On the hardware side, the detailed CIM accelerator design for incremental learning is illustrated. A workload-aware hardware resources assignment protocol is proposed to improve the throughput when the workload of weight gradient calculation is low. The software simulation results on CIFAR-100 dataset show that the proposed algorithm can effectively support incremental learning despite the device conductance variation exists. System-level benchmark shows that AILC could achieve 147×, 3.7×∼28.7×, 2.05×∼2.9× higher energy efficiency than Nvidia Titan-V GPU, RRAM-based CIM accelerators and edge TPU/GPU, respectively. Compared to the baselines, the throughput of AILC is improved by 2.0×∼2.2× on average with the hardware resources assignment protocol, which results in 4.1×∼21.4× higher throughput than edge TPU/GPU.

To efficiently deploy machine learning applications to the edge, compute-in-memory (CIM) based hardware accelerator is a promising solution with improved throughput and energy efficiency. Instant-on inference is further enabled by emerging non-volatile memory technologies such as resistive random access memory (RRAM). This paper reviews the recent progresses of the RRAM based CIM accelerator design. First, the multilevel states RRAM characteristics are measured from a test vehicle to examine the key device properties for inference. Second, a benchmark is performed to study the scalability of the RRAM CIM inference engine and the feasibility towards monolithic 3D integration that stacks RRAM arrays on top of advanced logic process node. Third, grand challenges associated with in-situ training are presented. To support accurate and fast in-situ training and enable subsequent inference in an integrated platform, a hybrid precision synapse that combines RRAM with volatile memory (e.g. capacitor) is designed and evaluated at system-level. Prospects and future research needs are discussed.

Compute-in-memory (CIM) is an attractive solution to address the “memory wall” challenges for the extensive computation in deep learning hardware accelerators. For custom ASIC design, a specific chip instance is restricted to a specific network during runtime. However, the development cycle of the hardware is normally far behind the emergence of new algorithms. Although some of the reported CIM-based architectures can adapt to different deep neural network (DNN) models, few details about the dataflow or control were disclosed to enable such an assumption. Instruction set architecture (ISA) could support high flexibility, but its complexity would be an obstacle to efficiency. In this article, a runtime reconfigurable design methodology of CIM-based accelerators is proposed to support a class of convolutional neural networks running on one prefabricated chip instance with ASIC-like efficiency. First, several design aspects are investigated: (1) the reconfigurable weight mapping method; (2) the input side of data transmission, mainly about the weight reloading; and (3) the output side of data processing, mainly about the reconfigurable accumulation. Then, a system-level performance benchmark is performed for the inference of different DNN models, such as VGG-8 on a CIFAR-10 dataset and AlexNet GoogLeNet, ResNet-18, and DenseNet-121 on an ImageNet dataset to measure the trade-offs between runtime reconfigurability, chip area, memory utilization, throughput, and energy efficiency.

Physarum polycephalum, a unicellular and multiheaded slime mould, can form highly efficient networks connecting separated food sources during the process of foraging. These adaptive networks exhibit a unique characteristic in that they are optimized without the control of a central consciousness. Inspired by this phenomenon, we present an efficient exploration and navigation strategy for a swarm of robots, which exploits cooperation and self-organisation to overcome the limited abilities of the individual robots. The task faced by the robots consists in the exploration of an unknown environment in order to find a path between two distant target areas. For the proposed algorithm (EAIPP), we experimentally present robustness tests and obstacle tests conducted to analyse the performance of our algorithm and compare the proposed algorithm with other swarm robot foraging algorithms that also focus on the path formation task. This work has certain significance for the research of swarm robots and Physarum polycephalum. For the research of swarm robotics, our algorithm not only can lead multirobot as a whole to overcome the limitations of very simple individual agents but also can offer better performance in terms of search efficiency and success rate. For the research of Physarum polycephalum, this work is the first one combining swarm robots and Physarum polycephalum. It also reveals the potential of the Physarum polycephalum foraging principle in multirobot systems.

The requirement of multilevel cell (MLC) resistive random access memory (RRAM) for computing is different than that for MLC storage. It generally requires a linearly spaced conductance median and an ultratight conductance distribution, as the column current are summed up for analog computation. In this article, 3-bit per cell RRAM that is suitable for accurate inference of a deep neural network (DNN) is demonstrated, with ultratight conductance distribution ( $5.3 \times $ and $4.4 \times $ , respectively, compared to the 3-bit per cell RRAM used as MLC storage.

Compute-in-memory (CIM) is a promising computing paradigm to accelerate the inference of deep neural network (DNN) algorithms due to its high processing parallelism and energy efficiency. Prior CIM-based DNN accelerators mostly consider full custom design, which assumes that all the weights are stored on-chip. For lightweight smart edge devices, this assumption may not hold. In this article, CIM-based DNN accelerators are designed and benchmarked under different chip area constraints. First, a scheduling strategy and dataflow for DNN inference is investigated when only part of the weights can be stored on-chip. Two weight reload schemes are evaluated: 1) reload partial weights and reuse input/output feature maps and 2) load a batch of input and reuse the partial weights on-chip across the batch. Then, system-level performance benchmark is performed for the inference of ResNet-18 on ImageNet data set. The design tradeoffs with different area constraints, dataflow, and device technologies [static random access memory (SRAM) versus ferroelectric field-effect transistor (FeFET)] are discussed.

Compute-in-memory (CIM) with emerging non-volatile memories (eNVMs) is time and energy efficient for deep neural network (DNN) inference. However, challenges still remain for DNN in-situ training with eNVMs due to the asymmetric weight update behavior, high programming latency and energy consumption. To overcome these challenges, a hybrid precision synapse combining eNVMs with capacitor has been proposed. It leverages the symmetric and fast weight update in the volatile capacitor, as well as the non-volatility and large dynamic range of the eNVMs. In this article, DNN in-situ training architecture with hybrid precision synapses is proposed and system level benchmarked is conducted. First, the circuit modules required for in-situ training with hybrid precision synapses are designed and the system architecture is proposed. Then, the impact of different weight precision configurations, weight transfer interval and limited capacitor retention time on training accuracy is investigated by incorporating hardware properties into Tensorflow simulation. Finally, the system-level benchmark is conducted at 32nm technology node in the modified NeuroSim simulator for hybrid precision synapse, in comparison with the baseline designs that are solely based on eNVMs or SRAM technology. The benchmark results show that CIM accelerator based on hybrid precision synapse achieves at least 3.07x and 2.89x better energy efficiency for training compared with its eNVM counterparts and SRAM technology at 32nm node, respectively. 227x and 33.8x better energy efficiency are obtained when compared to GPU and TPU. The scaling trend of hybrid precision synapse is projected towards 7nm node and comparison with state-of-the-art 7nm SRAM technology is made.

The multilevel resistive random access memory (RRAM)-based synaptic array can enable parallel computations of vector–matrix multiplication for machine learning inference acceleration; however, any conductance drift of the cell may induce an inference accuracy drop because the analog current is summed up along the column. In this article, the read disturb-induced conductance drift characteristic is statistically measured on a test vehicle based on 2-bit HfO2 RRAM array. The drift behavior of four states is empirically modeled by a vertical and lateral filament growth mechanism. Furthermore, a bipolar read scheme is proposed and tested to enhance the resilience against the read disturb. The modeled read disturb and proposed compensation scheme are incorporated into a VGG-like convolutional neural network for CIFAR-10 data set inference.

One of the main issues of EUV lithography is Line Edge Roughness (LER) on photo-resists, which significantly impacts yield at sub-30 nm pitches. In this work, an analytical model of LER is presented and analyzed for yield loss induced by open/short failures, cut mask defects, enhanced time dependent dielectrics breakdown (TDDB) failures for metal wires with different geometries, electro-migration (EM) impacts from the presence of LER on SRAM bitlines, and finally, LER impacts on functional errors. The model will be evaluated on single and double patterned designs with metal pitches of 24 and 28 nanometers. We show experimental results and give specific criteria in which LER thresholds can be relaxed without negatively impacting yield and path delay. This is a critical issue as higher LER tolerance allows exponential increase in throughput and thus reduces cost of fabrication.

Resistive RAM (RRAM) has been presented as a promising memory technology toward deep neural network (DNN) hardware design, with nonvolatility, high density, high ON/OFF ratio, and compatibility with logic process. However, prior RRAM works for DNNs have shown limitations on parallelism for in-memory computing, array efficiency with large peripheral circuits, multilevel analog operation, and demonstration of monolithic integration. In this article, we propose circuit-/device-level optimizations to improve the energy and density of RRAM-based in-memory computing architectures. We report experimental results based on prototype chip design of 128 × 64 RRAM arrays and CMOS peripheral circuits, where RRAM devices are monolithically integrated in a commercial 90-nm CMOS technology. We demonstrate the CMOS peripheral circuit optimization using input-splitting scheme and investigate the implication of higher low resistance state on energy efficiency and robustness. Employing the proposed techniques, we demonstrate RRAM-based in-memory computing with up to 116.0 TOPS/W energy efficiency and 84.2% CIFAR-10 accuracy. Furthermore, we investigate four-level programming with single RRAM device, and report the system-level performance and DNN accuracy results using circuit-level benchmark simulator NeuroSim.

Machine learning inference engine is of great interest to smart edge computing. Compute-in-memory (CIM) architecture has shown significant improvements in throughput and energy efficiency for hardware acceleration. Emerging nonvolatile memory (eNVM) technologies offer great potentials for instant on and off by dynamic power gating. Inference engine is typically pre-trained by the cloud and then being deployed to the field. There is a new security concern on cloning of the weights stored on eNVM-based CIM chip. In this paper, we propose a countermeasure to the weight cloning attack by exploiting the process variations of the periphery circuitry. In particular, we use weight fine-tuning to compensate the analog-to-digital converter (ADC) offset for a specific chip instance while inducing significant accuracy drop for cloned chip instances. We evaluate our proposed scheme on a CIFAR-10 classification task using a VGG- 8 network. Our results show that with precisely chosen transistor size on the employed SAR-ADC, we could maintain 88%~90% accuracy for the fine-tuned chip while the same set of weights cloned on other chips will only have 20~40% accuracy on average. The weight fine-tune could be completed within one epoch of 250 iterations. On average only 0.02%, 0.025%, 0.142% of cells are updated for 2-bit, 4-bit, 8-bit weight precisions in each iteration.

Fault diagnosis is of great significance to improve the production efficiency and accuracy of industrial robots. Compared with the traditional gradient descent algorithm, the extreme learning machine (ELM) has the advantage of fast computing speed, but the input weights and the hidden node biases that are obtained at random affects the accuracy and generalization performance of ELM. However, the level-based learning swarm optimizer algorithm (LLSO) can quickly and effectively find the global optimal solution of large-scale problems, and can be used to solve the optimal combination of large-scale input weights and hidden biases in ELM. This paper proposes an extreme learning machine with a level-based learning swarm optimizer (LLSO-ELM) for fault diagnosis of industrial robot RV reducer. The model is tested by combining the attitude data of reducer gear under different fault modes. Compared with ELM, the experimental results show that this method has good stability and generalization performance.

Deep neural network (DNN) training produces a large amount of intermediate data. As off-chip DRAM access is both energy and time consuming, sufficient on-chip buffer is preferred to achieve high energy efficiency for DNN accelerator designs. However, the low integration density and high leakage current of SRAM lead to large area cost and high standby power. The frequent refresh of embedded DRAM (eDRAM) degrades the energy efficiency due to its short refresh interval (40~100µs). In this paper, a dual-mode buffer memory that can operate in both volatile eDRAM mode and non-volatile ferroelectric RAM (FeRAM) mode is proposed, which is based on the CMOS compatible HfZr02 material. The functionality of the proposed dual-mode memory design is verified using SPICE simulation with the multi-domain Preisach model. A data lifetime-aware memory mode configuration protocol is proposed to optimize the buffer access energy. The architectural benchmark for DNN training shows 33.8%, 17.1 % and 109.4% higher energy efficiency than baseline designs with eDRAM, FeRAM and SRAM with the same buffer area, respectively. The chip standby power is reduced by 26.8x~47.5x and 1.5x~10.6x compared with the SRAM and eDRAM baselines. The chip area overhead of the dual-mode buffer design is 5.7%.