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With the development of integrated circuits, high power, and high integration chip array devices are facing the requirements of high heat flux and temperature uniformity. The micro-channel heat sink can meet the heat dissipation requirements of chip array devices with high heat flux, and the flow channel with fractal structure can achieve high temperature uniformity of chip array. In this study, the H-shaped fractal micro-channel structure was proposed to cooling the 4?4 chip (1 ? 1 mm) array. The interior fillet structure was introduced to optimize T-shaped and L-shaped corner structures in the fractal channel. The simulation results show that the overall pressure drop of micro-channel heat sink with is reduced 18.7%, and the maximum temperature difference of 4?4 chip array is less than 1.2? at 1000 W/cm2. The micro-channel heat sink with interior fillet structure interior fillet structure was fabricated and assembled, and the hydro-thermal performance was characterized by thermal test chip at different flow rates and heat fluxes. The experimental results show that the standard deviation of temperature of 4?4 chip array is less than 3.5? at 1000 W/cm2 and 480 ml per minute. The error between experimental and simulation data is within ?1.5%, which proves the reasonability of CFD modelling and simulation. Furthermore, the results demonstrate that by introducing interior fillet structure into the T-shaped and L-shaped structures could reduce pumping power and improve temperature uniformity of chip array, which can be applied to improve the performance of the chip array devices with high heat flux.

Power chips with high power dissipation and high heat flux have caused serious thermal management problems. Traditional indirect cooling technologies could not satisfy the increasing heat dissipation requirements. The embedded cooling directly inside the chip is the hot spot of the current research, which bears greater cooling potential comparatively, due to the shortened heat transfer path and decreased thermal resistance. In this study, the thermal behaviors of the power chips were demonstrated using a thermal test chip (TTC), which was etched with microchannels on its substrate’s backside and bonded with a manifold which also fabricated with silicon wafer. The chip has normal thermal test function and embedded cooling function at the same time, and its size is 7 × 7 × 1.125 mm3. This paper mainly discussed the influence of width of microchannels and the number of manifold channels on the thermal and hydraulic performance of the embedded cooling structure in the single-phase regime. Compared with the conventional straight microchannel structure, the cooling coefficient of performance (COP) of the 8×-50(number of manifold distribution channels: 8, microchannel width: 50 μm)structure is 3.38 times higher. It’s verified that the 8×-50 structure is capable of removing power dissipation of 300 W (heat flux: 1200 W/cm2) at a maximum junction temperature of 69.6 ℃ with pressure drop of less than90.8 kPa. This study is beneficial to promote the embedded cooling research, which could enable the further release of the power chips performance limited by the dissipated heat.

From the dawn of the Information Age thermal management technology has played a key role in the continuing miniaturization, performance improvements, and higher reliability of electronic systems. The key advantage of embedded, versus conventional cooling is a reduction in the number of thermal interfaces between the heat source and the heat sink. Considerable research efforts have been devoted to improving the heat transfer efficiency through embedded cooling. However, there is a lack of a universal test platform to characterize the thermal performance of the embedded structure. In this work, an integrated electrical test vehicle co-designed with embedded cooling is proposed for evaluating the cooling performance of the embedded microfluidic structure and the overall dimension of the vehicle is under $30 \times 15\times 2\ \text{mm}^{3}$ . It provides a tool for analyzing the performance of embedded cooling and proposes a method for further study of embedded cooling mechanism.

This study introduces an enhanced thermal management strategy for efficient heat dissipation from GaN power amplifiers with high power densities. The advantages of applying an advanced liquid-looped silicon-based micro-pin fin heat sink (MPFHS) as the mounting plate for GaN devices are illustrated using both experimental and 3D finite element model thermal simulation methods, then compared against traditional mounting materials. An IR thermography system was equipped to obtain the temperature distribution of GaN mounted on three different plates. The influence of mass flow rate on a MPFHS was also investigated in the experiments. Simulation results showed that GaN device performance could be improved by increasing the thermal conductivity of mounting plates’ materials. The dissipated power density of the GaN power amplifier increased 17.5 times when the mounting plate was changed from LTCC (Low Temperature Co-fired Ceramics) (k = 2 Wm−1 K−1) to HTCC (High-Temperature Co-fired Ceramics) (k = 180 Wm−1 K−1). Experiment results indicate that the GaN device performance was significantly improved by applying liquid-looped MPFHS, with the maximum dissipated power density reaching 7250 W/cm2. A thermal resistance model for the whole system, replacing traditional plates (PCB (Printed Circuit Board), silicon wafer and LTCC/HTCC) with an MPFHS plate, could significantly reduce θjs (thermal resistance of junction to sink) to its theoretical limitation value.

With the development of high-performance multi-core microprocessors, the increase in hotspots density poses a severe challenge to chip thermal management. Embedded cooling can improve the cooling performance at the chip level. However, the cooling efficiency will be deteriorated by the interaction of hotspots. This paper proposes the concept of thermal superposition effect based on the relationship between the cooling efficiency of two hotspots and their relative positions. The effective cooling area and superposition area describe the thermal characteristics and interaction of hotspots, and the superposition factor β evaluates the intensity of interaction. By optimizing the superposition factor, the average temperature reduces 22%. Moreover, the factor can predict the average temperature of hotspots within the error under14%. Therefore, the thermal superposition effect and factor β is an effective analysis tool in multi-hotspot cooling, simplifying the analysis process and making it possible to predict and optimize the interaction by experiment and finite element simulation.

As the critical dimension size of integrated circuits continues to decrease, the integration density increases dramatically, and they are facing sever heat dissipation challenges. Embedding microfluidic structure directly inside the chip is a promising approach for eliminating the relatively large heat fluxes in interlayer configurations. Considerable research efforts have been devoted to the design and optimization to obtain better cooling performance. Although the previous work analyzed the embedded cooling from different aspects, there are common points in the research contents. This paper refined the common contents in the research and proposed a multidimensional test vehicle. It can not only predict the thermal behavior of different electronic devices, but also evaluate cooling schemes composed of various microfluidic and manifold structures.The results show that the test vehicle can eliminate up to 5.4 kW / cm 2 of heat flux within 1 mm 2 , and control the total thermal resistance under 0.076 K · cm 2 / W . Therefore, the multidimensional test vehicle provides a useful tool for evaluating the thermo-hydraulic performance of embedded microfluidic cooling. Moreover, it offers a research method for improving the cooling potential through the integration of microfluidics and thermal analysis.

This paper presents micro-Pirani vacuum gauges using low-resistivity monocrystal silicon for the heaters and the heat sinks. We designed a new Pirani gauge with an embedded Wheatstone bridge made by thick-silicon resistors that allows an improvement in resolution and sensitivity. With the optimized Wheatstone bridge structure, the temperature coefficient of the gauges pressure measure decreases from 2.5%/°C to 0.74%/°C, and the resolution was optimized from 0.071 to 0.008 Torr at 1 Torr. In addition, the gauges were packaged into non-hermetic cavities by wafer-level AlGe eutectic bonding to undergo the wafer-dicing process, with sensitivity improved from 1.65 to 17.1 V/Torr at 1 Torr.

This paper proposes a performance-enhanced SiOx/Al corrugated micro-cantilever structure, which transfers heat to mechanical deformation. Analytical simulations are carried out using the Finite Element Method (FEM), compared to the traditional straight bi-material structure (TSBMS) with same lengthL, the corrugated bi-material structures (CBMS) have higher temperature response sensitivitySTand lower stiffness factor K. Furthermore, two types of cantilever was fabricated, and the test result verifies the change of the stiffness factorK. Finally, the thermal mechanical uncooled infrared focal plane array (FPA) with CBMS was fabricated, and the test results show that the bending response of the CBMS is about 2 times greater than TSBMS with same length. The CBMS proposed in this paper could be used widely in MEMS apparatus field based on bimaterial microcantilever.

This paper presents a wafer-level packaged MEMS (Micro-electromechanical Systems) Pirani gauge with surrounded heat sinks with improved characteristics during the low limit of the cavity vacuum. Different to the reported gauges in other papers, it has four heat sinks, and one of these is the cap of the wafer-level package. And it utilizes two heaters and two constant resistors to construct an Whetstone Bridge, two meander-shaped suspended silicon coils is set as the heaters and two isolated comb-shaped silicon structures as the dual-lateral heat sinks. In addition, the substrate and capped wafers are used as dual-vertical heat sinks. The gauge is finally realized with the volume 1.4mm×1.2mm×0.5mm using the CMOS (Complementary Metal Oxide Semiconductor)-MEMS compatible process. The gauge was measured twice before and after wafer-level packaging. It denotes that with the introduction of the capped heat sink, the device bears a better sensitivity compared to the intermediate device before packaging. With a hole on the edge of the device, the gauge could be widely and flexibly used for the characterization of vacuum packaged MEMS devices.

Vladimir Nabokov was the greatest bilingual writer of the 20th century. China's Nabokov research has experienced three stages include the germination in 1980s, Translation heat in 1990s and the climax with the "Lolita heat" at the beginning of the 21st century. Compared with abroad Nabokov study, China's research has made certain academic achievements, but also there is a huge space to fill and it has broad research prospects. Keywords—Nabokov; Translation; research; China

After Herta Muller won the 2009 Nobel Prize for Literature and Mo Yan won the 2012 Nobel Prizefor Literature winner, these two writers have attracted a lot of controversy. The controversy focused on narrow nationality on literary content performance and political themes. Nationality is the essence of a writer to live on and the theme presents the ideology of its work. Nobel Prize awards has its own criteria in the scale for the Nationality and subject tendentiousness, Herta Muller and Mo Yan’s Nationality and political themes are not complementary, it is a contradictory unity in the pattern of text, which is due to the complexity of the thought and the local identity of the writers. Keywords—Herta Muller; Mo Yan; ethos; paradox

Ultra-low pressure application of Pirani gauge needs significant improvement of sensitivity and expansion of measureable low pressure limit. However, the performance of Pirani gauge in high vacuum regime remains critical concerns since gaseous thermal conduction with high percentage is essential requirement. In this work, the heat transfer mechanism of micro-Pirani gauge packaged in a non-hermetic chamber was investigated and analyzed compared with the one before wafer-level packaging. The cavity effect, extremely important for the efficient detection of low pressure, was numerically and experimentally analyzed considering the influence of the pressure, the temperature and the effective heat transfer area in micro-Pirani gauge chamber. The thermal conduction model is validated by experiment data of MEMS Pirani gauges with and without capping. It is found that nature gaseous convection in chamber, determined by the Rayleigh number, should be taken into consideration. The experiment and model calculated results show that thermal resistance increases in the molecule regime, and further increases after capping due to the suppression of gaseous convection. The gaseous thermal conduction accounts for an increasing percentage of thermal conduction at low pressure while little changes at high pressure after capping because of the existence of cavity effect improving the sensitivity of cavity-effect-influenced Pirani gauge for high vacuum regime.

As the costs of packaging and testing account for a substantial portion of microelectromechanical system (MEMS) devices, an effective and convenient characterization method is urgent to be investigated to lower the cost. In this paper, an electrical test method was utilized, and the test key used for a four-probe current-voltage test was designed to monitor the quality of the AuSn eutectic bonding. The electrical test can directly detect whether or not voids existed in the bonding layer. The difference in alloy state, for example, the existence of the (Au, Ni) 3Sn2 phase confirmed by the scanning electron microscope and energy dispersive x-ray spectroscopy test, can also be reflected by resistivity variation. The electrical test can be implemented automatically and conveniently unlike other characterization methods. Therefore, it is suitable to be applied in quality inspection in industrial production.

With the trend of developments of infrared-focal plane array (FPA) which is particularly pronounced in many applications, in this paper, we demonstrated an uncooled infrared (8~14μm) camera based on the optically read-out Bi-material Infrared FPA. We reported on the fabrication and characterization of arrays of bimaterial microcantilevers. On the basis of opto-mechanical effect and micro electromechanical system (MEMS) technology, a substrate-free FPA with the thermal isolated structure SiNx and Au for uncooled infrared imaging is developed, with 49.5μm×49.5μm of the pixel and 240×240 array, moreover, the camera had an average noise equivalent temperature difference (NETD) and a response time of 100mK and 100ms at 7Pa atmospheric pressure, respectively.

With the trend of minimization of Fourier transform spectrometer (FTS) which is particularly pronounced in many applications, a model of a micro FTS with no moving parts is proposed and analyzed. During analyzng, the gradients which mainly introduce phase error are accounted. Based on these assumptions and the improved Mertz phase correcting method, the spectrum of signal is simulated with real extended light source. The resolution can be up to 3.43nm@800nm, with high signal-to-noise ratio (SNR) limiting resolving ability 6.8dB. In addition, the fabrication method of components are illuminated and demonstrated, which can not only make it bear some advantages over conventional micro dispersive spectrometers, but also afford some new concepts on the design of spectrometers with improved performance.

Micro-devices with a bi-material-cantilever (BMC) commonly suffer initial curvature due to the mismatch of residual stress. Traditional corrective methods to reduce the residual stress mismatch generally involve the development of different material deposition recipes. In this paper, a new method for reducing residual stress mismatch in a BMC is proposed based on various previously developed deposition recipes. An initial material film is deposited using two or more developed deposition recipes. This first film is designed to introduce a stepped stress gradient, which is then balanced by overlapping a second material film on the first and using appropriate deposition recipes to form a nearly stress-balanced structure. A theoretical model is proposed based on both the moment balance principle and total equal strain at the interface of two adjacent layers. Experimental results and analytical models suggest that the proposed method is effective in producing multi-layer micro cantilevers that display balanced residual stresses. The method provides a generic solution to the problem of mismatched initial stresses which universally exists in micro-electro-mechanical systems (MEMS) devices based on a BMC. Moreover, the method can be incorporated into a MEMS design automation package for efficient design of various multiple material layer devices from MEMS material library and developed deposition recipes.