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The investigation of two-dimensional (2D) materials has advanced into practical device applications, such as cascaded logic stages. However, incompatible electrical properties and inappropriate logic levels remain enormous challenges. In this work, a doping-free strategy is investigated by top gated (TG) MoS2 field-effect transistors (FETs) using various metal gates (Au, Cu, Ag, and Al). These metals with different work functions provide a convenient tuning knob for controlling threshold voltage (Vth) for MoS2 FETs. For instance, the Al electrode can create an extra electron doping (n-doping) behavior in the MoS2 TG-FETs due to a dipole effect at the gate-dielectric interface. In this work, by achieving matched electrical properties for the load transistor and the driver transistor in an inverter circuit, we successfully demonstrate wafer-scale MoS2 inverter arrays with an optimized inverter switching threshold voltage (VM) of 1.5 V and a DC voltage gain of 27 at a supply voltage (VDD) of 3 V. This work offers a novel scheme for the fabrication of fully integrated multistage logic circuits based on wafer-scale MoS2 film.

Contact engineering is of critical importance for two-dimensional (2D) transition metal dichalcogenide (TMD)-based devices. However, there are only a few solutions to overcome this obstacle because of the complexity of the TMD-contact interface. In this work, we propose a novel method using a soft plasma treatment followed by the seamless deposition of a metal electrode to reduce the contact resistance of MoS2 field effect transistors (FETs). The treated FETs exhibit three times higher mobility than the control FETs without plasma treatment. The soft plasma treatment can remove the facial sulfur atoms and expose the middle Mo atoms so that they come into direct contact with the metal electrode, thus greatly improving the contact behavior. First-principles calculation is also performed to support the experimental results. Our potentially scalable strategy can be extended to the whole family of TMD based FETs to provide a possible route of device processsing technology for 2D device application.

In this article, accurate physical and SPICE model of wafer-level monolayer molybdenum disulfide (MoS2) device are developed to guide the devices and circuits design, which is the foundation of high-performance analog chip design. Moreover, the proposed model considers the non-ideality of thin films and the influence of Schottky contact with higher accuracy. The mean percentage error (MPE) of the physical model simulation and measurement results is 4.49%. Based on the SPICE model implemented in this article, the amplifier circuit and current amplifying circuits are implemented to verify the manufacturing process and accuracy of the device models, which shows the MoS2 is potential material to realize industrial applications. The MPE of the SPICE model simulation and measurement results is within 7.00% which can be utilized for our analog circuit design.

We demonstrate dual-gated (DG) MoS2 field effect transistors (FETs) in which the degraded switching performance of multilayer MoS2 can be compensated by the DG structure. It produces large current ...

Two-dimensional heterojunctions exhibit many unique features in nanoelectronic and optoelectronic devices. However, heterojunction engineering requires a complicated alignment process and some defects are inevitably introduced during material preparation. In this work, a laser scanning technique is used to construct a lateral WSe2 p-n junction. The laser-scanned region shows p-type behavior, and the adjacent region is electrically n-doped with a proper gate voltage. The laser-oxidized product WOx is found to be responsible for this p-type doping. After laser scanning, WSe2 displays a change from ambipolar to unipolar p-type property. A significant photocurrent emerges at the p-n junction. Therefore, a self-powered WSe2 photodetector can be fabricated based on this junction, which presents a large photoswitching ratio of 106, a high photoresponsivity of 800 mA W-1, and a short photoresponse time with long-term stability and reproducibility. Therefore, this selective laser-doping method is prospective in future electronic applications.

Compared with the semimetallic single layer graphene (SLG), large-sized bilayer graphene with a desired stacking order is extremely useful in the twilight of two-dimensional electronics era. Howeve...

In this letter, we demonstrate a novel junction field-effect transistor by transferring MoS2 onto a silicon-on-insulator (SOI) substrate to control the thin Si channel. By combining high light absorption coefficient in MoS2 with high internal gain in thin Si channel, the device can be used for photodetection and can achieve high responsivity up to $\sim {1.78}\times {10}^{4}$ A/W, high detectivity over ${3}\times {10}^{13}$ Jones, and short response time down to 1.44 ms. Furthermore, unlike the conventional SOI photodetector, which is only sensitive to UV light, the response spectrum of our proposed device peaks in visible/near-infrared region, which is interesting for imaging and optical communication applications.

Triggered by the pioneering research on graphene, the family of two-dimensional layered materials (2DLMs) has been investigated for more than a decade, and appealing functionalities have been demonstrated. However, there are still challenges inhibiting high-quality growth and circuit-level integration, and results from previous studies are still far from complying with industrial standards. Here, we overcome these challenges by utilizing machine-learning (ML) algorithms to evaluate key process parameters that impact the electrical characteristics of MoS2 top-gated field-effect transistors (FETs). The wafer-scale fabrication processes are then guided by ML combined with grid searching to co-optimize device performance, including mobility, threshold voltage and subthreshold swing. A 62-level SPICE modeling was implemented for MoS2 FETs and further used to construct functional digital, analog, and photodetection circuits. Finally, we present wafer-scale test FET arrays and a 4-bit full adder employing industry-standard design flows and processes. Taken together, these results experimentally validate the application potential of ML-assisted fabrication optimization for beyond-silicon electronic materials., Here, the authors demonstrate the application of machine learning to optimize the device fabrication process for wafer-scale 2D semiconductors, and eventually fabricate digital, analog, and optoelectrical circuits.

Two-dimensional heterojunctions exhibit many unique features in nanoelectronic and optoelectronic devices. However, heterojunction engineering requires a complicated alignment process and some defects are inevitably introduced during material preparation. In this work, a laser scanning technique is used to construct a lateral WSe

Semiconductive two dimensional (2D) materials have attracted significant research attention due to their rich band structures and promising potential for next-generation electrical devices. In this work, we investigate the MoS2 field-effect transistors (FETs) with a dual-gated (DG) architecture, which consists of symmetrical thickness for back gate (BG) and top gate (TG) dielectric. The thickness-dependent charge transport in our DG-MoS2 device is revealed by a four-terminal electrical measurement which excludes the contact influence, and the TCAD simulation is also applied to explain the experimental data. Our results indicate that the impact of quantum confinement effect plays an important role in the charge transport in the MoS2 channel, as it confines charge carriers in the center of the channel, which reduces the scattering and boosts the mobility compared to the single gating case. Furthermore, temperature-dependent transfer curves reveal that multi-layer MoS2 DG-FET is in the phonon-limited transport regime, while single layer MoS2 shows typical Coulomb impurity limited regime.

Author(s): Xu, H; Zhang, H; Liu, Y; Zhang, S; Sun, Y; Guo, Z; Sheng, Y; Wang, X; Luo, C; Wu, X; Wang, J; Hu, W; Xu, Z; Sun, Q; Zhou, P; Shi, J; Sun, Z; Zhang, DW; Bao, W | Abstract: Semiconductive transition metal dichalcogenides (TMDs) have been considered as next generation semiconductors, but to date most device investigations are still based on microscale exfoliation with a low yield. Wafer scale growth of TMDs has been reported but effective doping approaches remain challenging due to their atomically thick nature. This work reports the synthesis of wafer-scale continuous few-layer PtSe2 films with effective doping in a controllable manner. Chemical component analyses confirm that both n-doping and p-doping can be effectively modulated through a controlled selenization process. The electrical properties of PtSe2 films have been systematically studied by fabricating top-gated field effect transistors (FETs). The device current on/off ratio is optimized in two-layer PtSe2 FETs, and four-terminal configuration displays a reasonably high effective field effect mobility (14 and 15 cm2 V−1 s−1 for p-type and n-type FETs, respectively) with a nearly symmetric p-type and n-type performance. Temperature dependent measurement reveals that the variable range hopping is dominant at low temperatures. To further establish feasible application based on controllable doping of PtSe2, a logic inverter and vertically stacked p–n junction arrays are demonstrated. These results validate that PtSe2 is a promising candidate among the family of TMDs for future functional electronic applications.