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Monolithic three‐dimensional (M3D) integration advances integrated circuits by enhancing density and energy efficiency. Ferroelectric thin‐film transistors (Fe‐TFTs) attract attention for neuromorphic computing and back‐end‐of‐the‐line (BEOL) compatibility. However, M3D faces challenges like increased runtime temperatures due to limited heat dissipation, impacting system reliability. This work demonstrates the effect of temperature impact on single‐gate (SG) Fe‐TFT reliability. SG Fe‐TFTs have limitations such as read‐disturbance and small memory windows, constraining their use. To mitigate these, dual‐gate (DG) Fe‐TFTs are modeled using technology computer‐aided design, comparing their performance. Compute‐in‐memory (CIM) architectures with SG and DG Fe‐TFTs are investigated for deep neural networks (DNN) accelerators, revealing heat's detrimental effect on reliability and inference accuracy. DG Fe‐TFTs exhibit about 4.6x higher throughput than SG Fe‐TFTs. Additionally, thermal effects within the simulated M3D architecture are analyzed, noting reduced DNN accuracy to 81.11% and 67.85% for SG and DG Fe‐TFTs, respectively. Furthermore, various cooling methods and their impact on CIM system temperature are demonstrated, offering insights for efficient thermal management strategies.

The developments in the nascent field of artificial-intelligence-of-things (AIoT) relies heavily on the availability of high-quality multi-dimensional data. A huge amount of data is being collected in this era of big data, predominantly for AI/ML algorithms and emerging applications. Considering such voluminous quantities, the collected data may contain a substantial number of outliers which must be detected before utilizing them for data mining or computations. Therefore, outlier detection techniques such as Mahalanobis distance computation have gained significant popularity recently. Mahalanobis distance, the multivariate equivalent of the Euclidean distance, is used to detect the outliers in the correlated data accurately and finds widespread application in fault identification, data clustering, singleclass classification, information security, data mining, etc. However, traditional CMOS-based approaches to compute Mahalanobis distance are bulky and consume a huge amount of energy. Therefore, there is an urgent need for a compact and energy-efficient implementation of an outlier detection technique which may be deployed on AIoT primitives, including wireless sensor nodes for in-situ outlier detection and generation of high-quality data. To this end, in this paper, for the first time, we have proposed an efficient Ferroelectric FinFET-based implementation for detecting outliers in correlated multivariate data using Mahalanobis distance. The proposed implementation utilizes two crossbar arrays of ferroelectric FinFETs to calculate the Mahalanobis distance and detect outliers in the popular Wisconsin breast cancer dataset using a novel inverter-based threshold circuit. Our implementation exhibits an accuracy of 94.1% which is comparable to the software implementations while consuming a significantly low energy (27.2 pJ).

Modern System-on-Chip (SoC) architectures necessitate low-voltage (LV) core transistors featuring excellent digital, analog, and radio frequency (RF) properties, as well as thick oxide transistors serving as robust I/O buffers and high-voltage (HV) transistors essential for efficient power management. This study presents a comprehensive DC to RF characterization, a detailed modeling strategy, and subsequent model parameter extraction for commercially produced LV and HV Fin Field Effect Transistors (FinFETs) at 14/16 nm technology. The industry-standard BSIM-CMG compact model is modified to accurately capture the characteristics of the HV FinFET devices integrated with the digital LV FinFETs for SoC applications. A detailed analysis of the DC, analog, and RF performance of LV, I/O, and HV FinFETs compared to the contemporary planar CMOS technology is performed. The large-signal performance of the device is evaluated using the developed model and validated with the measured data. Finally, a concise overview of the performance indicators associated with the modeled device is also presented.

This study introduces a new design for a low noise amplifier (LNA) consisting of two stages taking advantage of the inherent lossy properties of the input matching components. By doing this, the design balances the minimum noise figure (NF) and stability, eliminating the complexities and challenges introduced by feedback networks. Furthermore, the integration of the low-pass filter (LPF) into the design as a noise-matching network ensures improved performance across both the amplifier stages. A comprehensive analytical study is also introduced to delve deep into the relationship between critical LNA parameters, such as stability and noise figures, and the internal resistance of input-matching inductors. Two C-band LNAs are compared in terms of stability using indigenous $0.25~\mu \text{m}$ GaN technology. The designs are substantiated by fabricating two LNA MMICs for a 5–7 GHz frequency range, having a minimum NF of 1.3 dB and 1.5 dB, with a gain of 15 dB and 16 dB at 6 GHz, respectively. The study reveals that using the proposed approach, there is an overall improvement in NF of 0.2 dB within the frequency of operation. The work entails a way to remove the feedback network in the LNA leading to an improved NF.

Abstract Advancements in AI led to the emergence of in-memory-computing architectures as a promising solution for the associated computing and memory challenges. This study introduces a novel in-memory-computing (IMC) crossbar macro utilizing a multi-level ferroelectric field-effect transistor (FeFET) cell for multi-bit multiply and accumulate (MAC) operations. The proposed 1FeFET-1R cell design stores multi-bit information while minimizing device variability effects on accuracy. Experimental validation was performed using 28 nm HKMG technology-based FeFET devices. Unlike traditional resistive memory-based analog computing, our approach leverages the electrical characteristics of stored data within the memory cell to derive MAC operation results encoded in activation time and accumulated current. Remarkably, our design achieves 96.6% accuracy for handwriting recognition and 91.5% accuracy for image classification without extra training. Furthermore, it demonstrates exceptional performance, achieving 885.4 TOPS/W–nearly double that of existing designs. This study represents the first successful implementation of an in-memory macro using a multi-state FeFET cell for complete MAC operations, preserving crossbar density without additional structural overhead.

Cryogenic CMOS circuits that efficiently connect the classical domain with the quantum world are the cornerstone in bringing large-scale quantum processors to reality. The major challenges are, however, the tight power budget (in the order of milliwatts) and small latency (in the order of microseconds) requirements that such circuits inevitably must fulfill when operating at cryogenic temperatures. In-memory computing (IMC) is rapidly emerging as an attractive paradigm that holds the promise of performing computations efficiently where the data does not need to move back and forth between the CPU and the memory. Hence, it overcomes the fundamental bottleneck in classical von Neumann architectures, which provides considerable savings in power and latency. In this work, for the first time, we propose and implement an end-to-end approach that investigates SRAM-based IMC for cryogenic CMOS. To achieve that, we first characterize commercial 5 nm FinFETs from 300 K down to 10 K. Then, we employ the first cryogenic-aware industry-standard compact model for the FinFET technology (BSIM-CMG) to empower SPICE to accurately capture how cryogenic temperatures alter the electrical characteristics of transistors (e.g., threshold voltage, carrier mobility, sub-threshold slope, etc.). Our key contributions span from (1) carefully calibrating the cryogenic-aware BSIM-CMG against commercial 5 nm FinFET measurements in which SPICE simulations come with an excellent agreement with the experimental data, (2) exploring how the robustness of SRAM cells against noise (during the hold, read, and write operations) changes at extremely low temperatures, (3) investigating how the behavior of SRAM-based IMC circuits changes at 10 K compared to 300 K, and (4) modeling the error probabilities of IMC circuits that are used to calculate the Hamming distance, which is one of the essential similarity calculations to perform classifications.

Quantum computing can enable novel algorithms infeasible for classical computers. For example, new material synthesis and drug optimization could benefit if quantum computers offered more quantum bits (qubits). One obstacle for scaling up quantum computers is the connection between their cryogenic qubits at temperatures between a few millikelvin and a few kelvin (depending on qubit type) and the classical processing system on chip (SoC) at room temperature ($300 \,\mathrm{K}$). Through this connection, outside heat leaks to the qubits and can disrupt their state. Hence, moving the SoC into the cryogenic part eliminates this heat leakage. However, the cooling capacity is limited, requiring a low-power SoC, which, at the same time, has to classify qubit measurements under a tight time constraint. In this work, we explore for the first time if an off-the-shelf SoC is a plausible option for such a task. Our analysis starts with measurements of state-of-the-art 5-nm fin-shaped field-effect transistors (FinFETs) at 10 and $300 \,\mathrm{K}$. Then, we calibrate a transistor compact model and create two standard cell libraries, one for each temperature. We perform synthesis and physical layout of a RISC-V SoC at $300 \,\mathrm{K}$ and analyze its performance at $10 \,\mathrm{K}$. Our simulations show that the SoC at $10 \,\mathrm{K}$ is plausible but lacks the performance to process more than a few thousand qubits under the time constraint.

This paper aims to provide insights into the thermal, analog, and RF attributes, as well as a novel modeling methodology, for the FinFET at the industry standard 5nm CMOS technology node. Thermal characterization shows that for a 165K change in temperature, the Sub-threshold Slope (SS) and threshold voltage vary by 69 % and ~70 mV, respectively. At room temperature, a single gate contacted n-FinFET RF device exhibits a cutoff and maximum oscillation frequency of ~100 GHz and ~170 GHz, respectively. Analog and RF Figures of Merit (FoMs) for 5 nm technology at a device level and their temperature sensitivity are also reported. The industry standard BSIM-CMG model is modified to capture the impact of self-heating (SH) and parasitics. The SH model is based on measured data, and the modeling approach renders it independent of other model parameters. To the authors’ knowledge, an iteration free approach to develop a model-card for RF applications is explained for the very first time. Excellent agreement between the measured data and the model indicates that our methodology is accurate and can be used for faster PDK development.

In this article, we propose a nontraditional design of dynamic logic circuits using fully-depleted silicon-on-insulator (FDSOI) FETs. FDSOI FET allows the threshold voltage ( $V_{\text {t}}$ ) to be adjustable (i.e., low- $V_{\text {t}}$ and high- $V_{\text {t}}$ states) by using the back gate (BG) bias. Our design utilizes the front gate (FG) and BG of an FDSOI FET as the input terminals and proposes the dynamic logic gates (like NAND, NOR, AND, OR, XOR, and XNOR) and circuits (like a half-adder and full-adder). It requires fewer transistors to build dynamic logic gates and achieves high performance with low power dissipation compared to conventional dynamic logic designs. The compact industrial model of FDSOI FET (BSIM-IMG) has been used to simulate dynamic logic gates and is fully calibrated to reproduce the 14 nm FDSOI FET technology node data. Calibration is performed for both electrical characteristics and process variations. The simulation results show an average improvement in transistor count, propagation delay, power, and power-delay product (PDP) of 23.43%, 57.16%, 47.05%, and 77.29%, respectively, compared to the conventional designs. Further, our design reduces the charge-sharing effect, which affects the drivability of the dynamic logic gates. In addition, we have analyzed the impact of the process, supply voltage, and load capacitance variations on the propagation delay of the dynamic logic family in detail. The results show that these variations have a minor impact on the propagation delay of the proposed FDSOI-based dynamic logic gates compared to the conventional dynamic logic gates.

With the emergence of the Internet of Things (IoT), deep neural networks (DNNs) are widely used in different domains, such as computer vision, healthcare, social media, and defense. The hardware-level architecture of a DNN can be built using an in-memory computing-based design, which is loaded with the weights of a well-trained DNN model. However, such hardware-based DNN systems are vulnerable to model stealing attacks where an attacker reverse-engineers (REs) and extracts the weights of the DNN model. In this work, we propose an energy-efficient defense technique that combines a ferroelectric field effect transistor (FeFET)-based reconfigurable physically unclonable function (PUF) with an in-memory FeFET XNOR to thwart model stealing attacks. We leverage the inherent stochasticity in the FE domains to build a PUF that helps to corrupt the neural network’s (NN) weights when an adversarial attack is detected. We showcase the efficacy of the proposed defense scheme by performing experiments on graph-NNs (GNNs), a particular type of DNN. The proposed defense scheme is a first of its kind that evaluates the security of GNNs. We investigate the effect of corrupting the weights on different layers of the GNN on the accuracy degradation of the graph classification application for two specific error models of corrupting the FeFET-based PUFs and five different bioinformatics datasets. We demonstrate that our approach successfully degrades the inference accuracy of the graph classification by corrupting any layer of the GNN after a small rewrite pulse.

In this work, we report the development of a new physics-based analytical model for current and charge characteristics of Double Channel (DC) Gallium Nitride High Electron Mobility Transistors (GaN-HEMTs). The model has at its core the self-consistent calculation of the charge densities, for both upper and lower channels, obtained from a solution of the Schrödinger and Poisson equations. Fermi-Dirac (FD) distribution together with 2D density of states is used for mobile carrier statistics in both the channels. Furthermore, drift-diffusion transport is used to compute the channel current using charge densities at channel extremities. Finally, the model is validated against TCAD simulation and experimental data for a DC-GaN-HEMT. The model, by virtue of its fully physics-based nature, precisely captures the charge screening effect in the lower channel without invoking any empirical clamping functions, unlike prior models, and also possesses the feature of being geometrically scalable.

This paper presents a comparative performance analysis of a single-stage GaAs Low-Noise Power Amplifier (LNPA) fabricated in a $0.25~\mu $ m pHEMT process to mitigate co-site interference across multiple frequencies in the L- and S-bands. We compare five different designs from 1.2 to 3.8 GHz, each offering a minimum bandwidth of 300 MHz. Designed bandwidth is sufficient to cover several popular 5G NR FR1 channels as well as suitable for carrier aggregation in the LTE bands. An Output 1-dB compression point (OP1dB) of 27.5 dBm, noise figure (NF) below 1 dB and an Output 3rd-order Intercept Point (OIP3) up to 40 dBm is achieved. Adjacent Channel Leakage Ratio (ACLR) measurements are performed at 2.5 GHz with a Peak to Average Power Ratio (PAPR) of 11.8 dB. We achieve an ACLR of −25 dBc at 25 dBm of output power for a 20 MHz, 16-QAM modulation signal, while the corresponding power added efficiency & Drain-efficiency (DE) are, on average, more than 47% & 50% respectively. An integrated Electro-Static-Discharge (ESD) limiter is also incorporated, which can tolerate up to 350 V Human Body Model (HBM) and 125 V Charged Device Model (CDM) without failure. The design occupies a footprint of only 0.325 mm2.

In this article, we propose a compact model for Negative Capacitance Nanosheet Field Effect Transistor (NC-NSFET) including quasi-ballistic transport for sub-7nm technology node. The model captures the electrical characteristics of NC-NSFET for different ferroelectric thicknesses. Further, it captures the reverse short channel effects of NCFET for different channel lengths with a single set of parameters. Also, we build a model for terminal charges of NC-NSFET using the core model and the earlier developed inner fringing charge model. Using our physics-based model, we find that quasi ballistic transport worsens the capacitance matching in NCFET compared to drift-diffusion only case. We validate the compact model for the drain current and the terminal charges with the TCAD results. The proposed compact model is computationally efficient and implemented in the Verilog-A code to enable SPICE circuit simulations. Finally, we demonstrate this by applying our model for NC-NSFET based CMOS inverter and SRAM circuit implementations in SPICE.

This Special Issue is dedicated to recent research in the field of compact modeling of semiconductor devices. This is the first J-EDS Special Issue on compact modeling. In the last years, a number of new semiconductor device structures, for electronic and photonic applications, have been developed. Compact models are needed for the incorporation of these new devices in integrated circuits. Therefore, a Special Issue was needed to present recent compact modeling solutions for semiconductor devices

In this paper, we propose a trench MOS architecture for the upcoming 5 nm node and beyond logic transistor. The intended device has a gate formed vertically downward, with added spacers along the gate to S/D sidewall. In doing so, the recessed device having longer channel length (than the defined gate footprint) would be a constructive approach to limit the short channel effects (SCE). The novel transistor has the potential to enable the scaling of gate length (footprint) less than 10 nm and contacted gate pitch below 32 nm, resulting in the smallest active area (on-wafer footprint) for a single device. Novel process steps are simulated depicting easier fabrication while the electrical analysis shows a better electrostatic control over any unwanted leakage flows. Along with the area scaling and SCE control, the planar upper surface allows a vertical integration. Growing another flipped device on top surface permits the designer to implement a logic circuit on a footprint of a single device, achieving ~50% area gain further. TCAD based simulations were performed to design and characterize the performances of an individual device and the vertical inverter.

Negative capacitance field-effect transistor (NCFET) addresses one of the key fundamental limits in technology scaling, akin to the non-scalable Boltzmann factor, by offering a sub-threshold swing below 60 mV/decade. In this paper, we investigate how the NCFET technology can open the doors not only for the continuation of Moore's law, which is approaching its end, but also for reviving Dennard's scaling, which stopped more than a decade ago. We study NCFET for the 7-nm FinFET technology node, from physics to processors and demonstrate that prior trends in processor design with respect to voltage and frequency can be revived with the NCFET technology. Our work focuses on answering the following three questions towards drawing the impact of NCFET technology on computing efficiency: In how far NCFET technology will enable processors: 1) to operate at higher frequencies without increasing voltage; 2) to operate at higher frequencies without increasing power density, which is substantial, because maintaining on-chip power densities under tight constraints due to limited cooling capabilities is inevitable; and 3) to operate at lower voltages, while still fulfilling performance requirements, which is substantial for the emerging Internet of Things, in which available power budgets for such devices are typically very restricted.

In this paper, a consistent DC to RF modeling solution for Al gallium nitride (GaN)/GaN high electron mobility transistors is demonstrated that is constructed around a surface-potential-based core. Expressions for drain current and intrinsic terminal charges in the form of surface-potential are used to simultaneously model the DC characteristics and the intrinsic capacitances of a commercial GaN device. Self-heating and trapping effects are incorporated to account for the non-linear nature of the device. We discuss the parameter extraction flow for some of the key model parameters that are instrumental in fitting the DC characteristics, which simultaneously determines the bias-dependent intrinsic capacitances and conductances that significantly eases the RF parameter extraction. Parasitic capacitances, gate finger resistance, and extrinsic bus-inductances are extracted, from a single set of measured non-cold-FET S-parameters, using the model process design kit. The extraction procedure is validated through overlays of broadband (0.5-50 GHz) S-parameters, load-pull and harmonic-balance (10 GHz) simulations against measured data, under multiple bias conditions to successfully demonstrate the model performance at large-signal RF excitations.

In nanoscale MOSFETs with sub-10 nm channels, the source-to-drain tunneling is expected to be a critical bottleneck, especially in III-V devices on account of their extremely low effective masses. Also, to maintain electrostatic integrity at extremely small gate lengths, the channels need to be made ultrathin. In such devices, the bandstructure of the channel material becomes thickness dependent due to quantum confinement effects, and deviates remarkably from that of the bulk material. In this paper, we use first principle density functional theory calculations to evaluate the variation of the effective mass and bandgap with channel thickness. Then, we perform semi-classical ballistic and full quantum non-equilibrium Green's function transport simulations to study the impact on source-to-drain tunneling in III-V nMOSFETs. We demonstrate that the severity of the expected degradation due to source-to-drain leakage is reduced significantly, when the beneficial impacts of change in bandstructure, and multi-valley transport are taken into account.

In this paper, we present a compact model for semiconductor charge and quantum capacitance in III-V channel FETs. With III-V being viewed as the most promising candidate for future technology node, a compact model is needed for their circuit simulation. The model presented in this paper addresses this need and is completely explicit and computationally efficient which makes it highly suitable for SPICE implementation. The proposed model is verified against the numerical solution of coupled Schrödinger-Poisson equation for FinFET with various channel thickness and effective mass.

In this paper, we report the noise measurements in the RF frequency range for ultrathin body and thin buried oxide fully depleted silicon on insulator (FD-SOI) transistors. We analyze the impact of back and front gate biases on the various noise parameters; along with discussions on the secondary effects in FD-SOI transistors which contribute to the thermal noise. Using calibrated TCAD simulations, we show that the noise figure changes with the substrate doping and buried oxide thickness.

An improved analytical model for flicker noise (1/f noise) in MOSFETs is presented. Current models do not capture the effect of high-trap density in the halo regions of the devices, which leads to significantly different bias dependence of flicker noise across device geometry. The proposed model is the first compact model implementation capturing such effect and show distinct improvements over other existing noise models. The model is compatible with BSIM6, the latest industry standard model for bulk MOSFET, and is validated with measurements from 45-nm low-power CMOS technology node.

In this paper, we present a physics-based compact model for low frequency noise in high electron mobility transistors (HEMTs). The model is derived considering the physical mechanisms of carrier number fluctuation and mobility fluctuation in the channel. The model is tunable and hence applicable to a wide range of HEMT devices of different geometries and construction. The model is in excellent agreement with experimental data and TCAD simulations.

Two turn-key surface potential-based compact models are developed to simulate multigate transistors for integrated circuit (IC) designs. The BSIM-CMG (common-multigate) model is developed to simulate double-, triple-, and all-around-gate FinFETs and it is selected as the world's first industry-standard compact model for the FinFET. The BSIM-IMG (independent-multigate) model is developed for independent double-gate, ultrathin body (UTB) transistors, capturing the dynamic threshold voltage adjustment with back gate bias. Starting from long-channel devices, the basic models are first obtained using a Poisson-carrier transport approach. The basic models agree with the results of numerical two-dimensional device simulators. The real-device effects then augment the basic models. All the important real-device effects, such as short-channel effects (SCEs), quantum mechanical confinement effects, mobility degradation, and parasitics are included in the models. BSIM-CMG and BSIM-IMG have been validated with hardware silicon-based data from multiple technologies. The developed models also meet the stringent quality assurance tests expected of production level models.