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5 results on '"Yukiko Umemoto"'

2. Ultra-Low-Standby Power 6T Single-port and 8T Dual-port SRAMs on 65 nm Silicon-on-Thin-Box (SOTB) for Smart IoT Applications

Author

Yoshiki Yamamoto, Shinji Tanaka, Hiroki Shinkawata, Yukiko Umemoto, Shiro Kamohara, Makoto Yabuuchi, Takumi Hasegawa, Kyoji Ito, Koji Nii, Yohei Sawada, and Yoshihiro Shinozaki

Subjects
010302 applied physics, Physics, Silicon, business.industry, Electrical engineering, chemistry.chemical_element, Port (circuit theory), 02 engineering and technology, 01 natural sciences, 020202 computer hardware & architecture, chemistry, Megabit, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Static random-access memory, Internet of Things, business, Standby power, Sleep mode, Access time
Abstract

In 65-nm Silicon-on-Thin-Box (SOTB) technology, we demonstrate fully functional embedded 6T single-port (SP) SRAM and 8T dual-port (DP) SRAM for Smart Internet-of-Things (IoT) applications. By using back-bias (BB) control in the sleep mode, 13.72 nW/Mbit (25.85 nW/Mbit) ultra-low standby power for SP (DP) SRAM is observed. Both are reduced to 1/1000 compared to the normal standby mode. The measured read access time of 128-kb SP (32-kb DP) SRAM with forward BB is 1.84 ns (1.64 ns) at 1.0 V overdrive and 25°C, which is over 2.5× (2.75×) faster than that of normal mode at 0.75 V with zero BB. Besides, inherent read/write disturbance issues in DP SRAM are also evaluated by test chips, confirmed there are no issues.

Published
2018

3. 28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique

Author

Koji Tanaka, Yukiko Umemoto, Yasumasa Tsukamoto, Kazuyoshi Okamoto, Shinji Tanaka, Kazutaka Mori, Jiro Ishikawa, Kazumasa Yanagisawa, Makoto Yabuuchi, Koji Nii, and Tetsuya Matsumura

Subjects
Imagination, Read-only memory, Hardware_MEMORYSTRUCTURES, Computer science, media_common.quotation_subject, CMOS, Hardware and Architecture, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Electrical and Electronic Engineering, Macro, Software, Random access, Access time, Voltage, media_common, Leakage (electronics)
Abstract

We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achieving both high-speed operation and low power consumption. It is also possible to overcome the inherent problem of crosstalk between the bitlines. The fabricated 128-kb ROM macro using 28-nm high- k and metal-gate CMOS bulk technology realizes 0.72 ns read access time at the typical 0.85-V supply voltage, which is comparable to that of recent high-speed embedded static random access memories. The measured dynamic power dissipation is reduced by 50% compared to the conventional 2T ROM. The standby leakage can also be reduced to half that of conventional macros.

Published
2014

4. An Internal Voltage Generation System of Flash Memory Module Embedded in a Microcontroller

Author

Yutaka Shinagawa, Yukiko Umemoto, Toshihiro Tanaka, Akira Kato, Takashi Yamaki, I. Nakamura, T. Shimozato, Hiroyuki Tanikawa, and Jiro Ishikawa

Subjects
Engineering, Hardware_MEMORYSTRUCTURES, Flash memory emulator, business.industry, Sense amplifier, Registered memory, Flash memory, Microcontroller, Memory cell, Hardware_INTEGRATEDCIRCUITS, business, Computer memory, Flash file system, Computer hardware
Abstract

We present a new internal voltage generation system of flash memory module embedded in a microcontroller. One of the features is wide range voltage generator for the evaluation of the memory cell, which is effective mainly at the development early stage. The second feature is new temperature dependency voltage generator matched to memory cell property for the improvement of reliability. The third is an auto-trimming system that arranges output of internal voltage generators with target values. Using embedded CPU the auto-trimming system suppresses voltage variations for many chips simultaneously, so we can reduce test cost and improve reliability of flash memory module in the stage of mass production

Published
2005

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