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To the best of our knowledge, currently the physical model based method is still an ill posed problem. Additionally, the image enhancement approaches also suffer from the texture preservation issue. Retinex-based approach is proved its effectiveness in image dehazing while the parameter should be turned properly. Therefore, in this paper, the particle swarm optimization (PSO) algorithm is firstly performed to optimize the parameter and the hazed image is converted into hue, saturation, intensity(HSI) for color compensation, In the other hand, the multi-scale local detail upgrading and the bilateral filtering approaches are designed to overcome the dehazing artefacts and edge preservation, which could further improve the overall visual effect of images. Experimental results on natural and synthetic images by using qualitative analysis and frequently used quantitative evaluation metrics illustrate the approving defogging effect of the proposed method. For instance, in a natural image road, our method achieves the higher e for 0.63, γ for 3.21 and H for 7.81, respectively and lower σ for 0.04. In a synthetic image poster, the higher PSNR for 18.17 and SSIM for 0.78 are also acquired compared to other explored approaches in this paper. Besides, the results performed on other underwater and aerial images in this study further demonstrates its defog effectiveness.

This paper applies the multi-layer graphene nanoribbon as a new prospective filler material for through silicon via to solve the complex heat problems in the 3-D integrated circuits. An equivalent thermal model for 3-D integrated circuits with the MLGNR-based through silicon via is presented in this work, which take lateral heat transfer of through silicon via into account. The experimental results show that the heat transfer performance of MLGNR-based through silicon via is better than the conventional Cu-based through silicon via. Furthermore, it is found that the temperature predicted by the proposed model are in good accordance with the ANSYS simulation, and the maximum relative deviation is less than 4.0%

In the past few years, thermal through silicon via (TTSV) has been experimentally investigated as an effective heat dissipation path. Although a lot of heat dissipation-related issues have been solved in three-dimensional integrated circuit (3D-IC), there are neglections in TTSV placement with non-uniform heat sources so far. In this study, a unique optimization is proposed to locate TTSV while effectively alleviating hot spots in 3D-IC. The thermal dissipation of non-uniform heat sources are studied using the finite element method. The simulation results show that the minimum temperature is reduced by 2.1% compared with peak temperature in the single-layer chip, and by 1.9% in the three-layer chip.

In recent studies, the physiological parameters derived from human vital signals are found as the status response of the heart and arteries. In this paper, we therefore firstly attempt to extract abundant vital features from photoplethysmography(PPG) signal, its multivariate derivative signals and Electrocardiogram(ECG) signal, which are verified its statistical significance in BP estimation through statistical analysis t-test. Afterwards, the optimal feature set are obtained by usnig mutual information coefficient analysis, which could investigate the potential associations with blood pressure. The optimized feature set are aid as an input to various machine learning strategies for BP estimation. The results indicates that AdaBoost based BP estimation model outperforms other regression methods. Concurrently, AdaBoost-based model is further analyzed by using the Histograms of Estimation Error and Bland-Altman Plot. The results also indicate the great BP estimation performance of the proposed BP estimation method, and it stays within the Advancement of Medical Instrumention(AAMI) standard. Regarding the British Hypertension Society (BHS), it achieves the grade A for DBP and grade B for MAP. Besides, the experimental result illustrated that our proposed BP estimation method could reduce the MAE and the STD, and improve the r for SBP, MAP and DBP estimation, respectively, which further demonstrates the feasibility of our proposed BP estimation method in this paper.

An analytical thermal model is developed for N-die stacked chips with integrated micro-channels cooling. The model is implemented with some mathematical software. Comparison of the temperature predicted by the proposed model with some computer fluid dynamics software numerical results show excellent agreement, and the maximal relative error is less than 4.0%.

Microchannel cooling is a promising technology for solving the three-dimensional integrated circuit thermal problems. However, the relationship between the microchannel cooling parameters and thermal behavior of the three dimensional integrated circuit is complex and difficult to understand. In this paper, we perform a detailed evaluation of the influence of the microchannel structure and the parameters of the cooling liquid on steady-state temperature profiles. The results presented in this paper are expected to aid in the development of thermal design guidelines for three dimensional integrated circuit with microchannel cooling.

We investigate the finite-temperature and zero quark chemical potential QCD chiral phase transition of strongly interacting matter within the two-flavor Nambu–Jona-Lasinio (NJL) model as well as the proper time regularization. We use two different regularization processes, as discussed in Refs. 36 and 37, separately, to discuss how the effective mass M varies with the temperature T. Based on the calculation, we find that the M of both regularization schemes decreases when T increases. However, for three different parameter sets, quite different behaviors will show up. The results obtained by the method in Ref. 36 are very close to each other, but those in Ref. 37 are getting farther and farther from each other. This means that although the method in Ref. 37 seems physically more reasonable, it loses the advantage in Ref. 36 of a small parameter dependence. In addition, we also, find that two regularization schemes provide similar results when T [Formula: see text] 100 MeV, while when T is larger than 100 MeV, the difference becomes obvious: the M calculated by the method in Ref. 36 decreases more rapidly than that in Ref. 37.

The inspection of the defects in LED chip has become a critical task for manufacturers in order to enhance product quality. In this paper, a new approach for the defect inspection of LED chip is presented, which uses both the features of defects and the generalized regression neural networks. The approach consists of following three steps. First of all, preprocess of LED chip image is performed by using the image operations such as image enhancement. Secondly, the chip image is divided into a lot of sub-regions, the features of each sub-region are extracted, the database of features is built. Thirdly, an initial structure of generalized regression neural network is constructed, then the neural network is trained by using the features in database. The generalized regression neural network has the ability to converge to the underlying function of the data with only few training samples available, and the additional knowledge needed to input by the user is relatively small. The experimental results show that the defect inspection approach in this paper can effectively identify the LED chips with defects.

The defects of LED wafer may be caused from the manufacturing environments such as contamination. The appearance of the defects can results in functional faults of LED wafer. Therefore, it is very necessary to detect the defects in LED wafer. In this paper, a new method is presented for the defect feature acquisition of LED wafer, the method uses region growing to segment the LED wafer image in order to acquire the defect features. The clustering strategy is added to the region growing for enhancing the acquisition precision of defect features. The defect features that have been obtained can be used to detect these defects of LED wafer. The method consists of following two steps. First of all, the original image of LED wafer is partitioned into several sub-blocks that are not overlapped, and then these sub-blocks are segmented by clustering strategy. Secondly, the whole wafer image is segmented by using region growing algorithm.

The circuits should be tested extensively during the production process, the power consumption in a circuit during test mode can be higher than that the consumption during normal operation mode. The circuits are usually designed for normal operation mode, which makes it important to consider power consumption during test mode, otherwise the higher power consumption during test mode may cause the circuits being damaged. In this paper, a new approach for the test pattern design of VLSI circuits is presented, the approach defines the weight values of primary inputs of circuits, makes use of both circuit structure information and pseudorandom test generation to produce the test patterns, such that the circuit has lower power consumption when the test patterns are applied to the circuit primary inputs. The experimental results show the approach in this paper can get significant power consumption reduction compared with conventional random test algorithm.

The crosstalk is induced between the elements in digital circuits due the increasing switching speeds and the decreasing in technology scaling. The crosstalk is caused by parasitic couplings between adjacent wires that include capacitance and inductance effects. The crosstalk can result in functional failures or timing problems. A test approach for the delay faults caused by crosstalk interferences in digital circuits is presented in this paper, the approach is based on decision diagrams and the selection of delay sensitive path. The static timing analysis is carried out to obtain the delay information about the paths, all aggressor lines are activated in the best possible way. The test vectors are generated by building a decision diagram and searching for the specific paths in the decision diagram. Experimental results show that the test approach proposed in this paper can generate the test vectors for the testable delay faults caused by crosstalk.

The main aspects for the test of system on chip (SoC) are designing testability architectures and solving the test scheduling. The test time of SoC can be reduced by using good test scheduling schemes. A test scheduling method based on cellular genetic algorithm is presented in this paper. In the method, the individuals are used to represent the feasible solutions of the test scheduling problem, the individuals are distributed over a grid or connected graph, the genetic operations such as selection and mutation are applied locally in some neighborhood of each individual. The test scheduling schemes are obtained by carrying out the evolutionary operations for the populations. A lot of experiments are performed for the SoC benchmark circuits, the experimental results show that the better test scheduling schemes can be obtained by the method in this paper.

The formal verification is able to check whether the implementation of a circuit design is functionally equivalent to an earlier version described at the same level of abstraction, it can show the correctness of a circuit design. A new circuit verification method based on cone-oriented circuit partitioning and decision diagrams is presented in this paper. First of all, the structure level of every signal line in a circuit is computed. Secondly, the circuit is partitioned into a lot of cone structures. The multiple-valued decision diagram corresponding to every cone structure is generated. The verification procedure is to compare the equivalence of the multiple-valued decision diagrams of two types of cone structures. Experimental results on a lot of benchmark circuits show the method presented in this paper can effectively perform the equivalence checking of circuits.

A new test pattern generation method for the stuck-at faults in VLSI circuits is presented in this paper, the method uses Hopfield neural networks and chaotic simulated annealing. The Hopfield neural network corresponding to a digital circuit is built, the test patterns of faults in digital circuits are produced by computing the optima of the energy function. A chaotic simulated annealing algorithm is designed, which combines the features of chaotic systems and conventional simulated annealing, it is able to take the advantages of the stochastic properties and global search ability of chaotic system. The algorithm is used to compute the optima of the energy function of neural networks in order to produce the test patterns of faults. Experimental results show that the test pattern generation method proposed in this paper can produce the test patterns in short time for both single stuck-at faults and multiple stuck-at faults in digital circuits.

A new test generation method for the bridging faults in digital circuits is proposed in this paper, the method is based on shared binary decision diagram. The shared binary decision diagram can represent many logic functions simultaneously by sharing isomorphic subgraphs, it is used to represent the digital circuits with multiple primary outputs. The binary decision diagram is constructed respectively for the normal circuit and faulty circuit having a bridging fault. The test vectors of the bridging fault can be produced by a XOR operation of the two binary decision diagrams. The experimental results on a lot of benchmark circuits demonstrate that the test method proposed in this paper can get the test vectors of the bridging faults if the faults are testable.

The crosstalk fault in VLSI circuits is one of the interference effects being caused by parasitic capacitance and inductance coupling, it can lead to functional errors of circuits. It is necessary to detect the crosstalk faults in order to insure the functions of circuits. A new test method for crosstalk faults in VLSI circuits based on multiple-valued decision diagrams is presented in this paper, the test vectors of crosstalk faults are generated by building a multiple-valued decision diagram that is a difference operation of the two multiple-valued decision diagrams corresponding to the normal circuit and faulty circuit, respectively. One advantage of the test method is that it can get all test vectors of a given crosstalk fault, therefore for a digital circuit, the test set with minimal number of test vectors can be obtained. Experimental results on a lot of digital circuits demonstrate the feasibility of the method proposed in this paper.

The more signal path ways close to each other in digital circuits, the greater the coupling effects. The coupling effects can led to an increasing number of signal integrity related faults such as crosstalk faults. In this paper, the glitch faults of crosstalk effects are studied. First of all, the test vector generation using signal paths of circuits is given. Secondly, a new test method for crosstalk faults in digital circuits is presented, which is based on the genetic algorithm with niche. The test method can detect the maximal crosstalk effects, i.e. the test vectors to be produced is to switch a set of aggressors that maximizes the switching of total coupling effects. The test method is also used to produce the test vectors of multiple crosstalk faults. The experimental results show that the method proposed in this paper can get the test vectors of the multiple crosstalk faults if the faults are testable.

The study aimed to review the treatment and prognosis of acute obstruction of colorectal cancers and to compare different treatment strategies of those cancers, and to evaluate the risk factors affecting perioperative complications.Clinical data of 184 patients with acute obstruction of colorectal cancer undergone operation were analyzed retrospectively.A total of 184 patients with acute obstruction of colorectal cancer was collected in this study, including 58 patients with proximal and 126 patients of distal colorectal cancers. Perioperative death occurred in 2/58 patients (3.4%) with distal colorectal cancer and 6/126 cases (4.8%) of distal colorectal cancer (P0.05). The overall perioperative complications in the two groups were not significantly different (P = 0.794). Among the 58 patients with proximal colorectal cancer, one patient underwent colostomy, but among the 126 patients with distal colorectal cancer, 41 patients underwent colostomy, showing a significant difference between the two groups (P = 0.002). ASA scores (grade 3 - 4), elderly age (≥ 70 years) and colon perforation peritonitis were independent prognostic factors associated with perioperative mortality and morbidity. Patients in the self-expandable metallic stent (SEMS) group had a significantly shorter hospital stay (25.4 ± 8.3) d than that in the emergency surgery group (32.8 ± 16.4) d, (P = 0.039).Endoscopic stent implantation provides an acceptable modality of palliation for acute proximal large bowel obstruction caused by malignancies. In acute colorectal cancer obstruction, SEMS can provide a minimally invasive management compared with surgical intervention.

The aim of this study was to review the etiology and pathogenesis of patients who underwent surgery for mechanical bowel obstruction. The treatment and prognosis of bowel obstructions caused by intra-abdominal tumors were compared with those due to other causes.The clinical data of 203 patients with mechanical bowel obstruction undergoing operation were analyzed retrospectively. The tumor cases were classified as group I, and all other cases as group II. A range of factors were investigated to estimate the postoperative outcome: gender, age, comorbidities, symptoms and findings of physical and radiological examinations, sites of the obstruction, etiology, therapeutic approach, postoperative complications and mortality.Group I included 73 patients and Group II 130. Large bowel carcinoma and peritoneal adhesions were the most common causes of Group I and II, contributing 58 and 86 of all cases, respectively. There was no significant difference in terms of gender between the two groups, but the rate of elderly (≥ 70 years) patients was significantly higher (53.4%) than that of the70 years old patients (35.4%) (P = 0.012). There was a significant difference between the patients with previous surgical operation history in the tumor group (23.3%) and non-tumor group (58.5%) (P0.001). In the 73 cases of the tumor group, the obstruction was located in the large bowel in 58 cases (79.5%), small bowel in 12 cases (16.4%), both small and large bowels in 2 cases (2.7%) and gastric cancer invading the splenic flexure of colon in 1 case, while in the non-tumor group, 111 cases (85.4%) of the obstruction was located in the small bowel and 19 cases (14.6%) and in the large bowel (P0.001). Sixty-six cases (90.4%) of the tumor-group underwent intestinal segment excision and 21 cases (28.8%) underwent intestinal fistulation in the tumor group, but in the non-tumor group 61 cases (46.9%) underwent intestinal segment excision and 5 cases (3.8%) underwent intestinal fistulation (all P0.001). The hospital stay was (18 ± 6) days in the tumor group and (11 ± 3) days in the non-tumor group (P0.01). The complication rate (P = 0.104) and mortality rate (P = 0.187) were not significantly different between the two groups.Tumor mechanical bowel obstruction is more frequently seen in patients in elder age, with colorectal location and without previous operation history. CT scan may provide effective diagnosis and ascertain the presence of the malignant obstruction. Intestinal fistulation is more often needed in patients with tumor intestinal obstruction and endoscopic stenting is a safe option in selected patients with tumor intestinal obstruction.

To evaluate the risk factors affecting the early postoperative outcomes in patients with small bowel obstruction.Clinical data of 193 patients with small bowel obstruction undergone operation were analyzed retrospectively. A range of factors were investigated to estimate postoperative outcome, including gender, age, comorbidities, etiology of obstruction, presence of strangulated bowel (viable or nonviable), leukocyte count, temperature, and heart rate. Logistic regression analysis was used to study the prognostic value of each significant variable in terms of postoperation.The major causes of small bowel obstruction were adhesion and hernia, contributing 38.9% and 37.8% of all cases, respectively. Strangulation occurred in 42.0% and caused nonviable bowel in 23.3% of obstructing episodes. Elderly (or=70 years), diabetes, malignant tumors WBC15x10(9)/L were independent significant factors associated with bowel strangulation. The overall complication rate was 16.1%, the 30-day mortality was 4.1%, and the median postoperative hospital stay was 13 days. Ageor=70 years and bowel resection were significantly associated with postoperative complications in the univariate analysis. Only elderly and malignant obstruction were significantly associated with operative mortality in multivariate logistic regression.Surgery for small bowel obstruction is still associated with significant mortality and morbidity. Elderly is significantly associated with an increased incidence of strangulation, operative mortality, and complications.