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Current filament (CF)-related double-hysteresis ${I}$ – ${V}$ behavior and holding current, ${I} _{\text {HOLD}}$ , are analyzed using experiments and 3-D technology computer-aided design (TCAD) simulation in silicon-controlled rectifiers (SCR) for system-level electrostatic discharge (ESD) protection. Our 3-D TCAD methodology uses up and down quasi-dc current sweeps to reveal a memory effect in the current density distribution along the device width. ${I} _{\text {HOLD}}$ is related to the smallest possible CF where the self-sustaining SCR action takes place during down current sweep. ${I} _{\text {HOLD}}$ exhibits a nontrivial dependence on device width, depending on whether a CF is created or not. Analyzing devices of different layouts shows that ${I} _{\text {HOLD}}$ values determined from experiments and 3-D TCAD are almost layout-independent and substantially lower than those evaluated from 2-D TCAD. ${I} _{\text {HOLD}}$ calculated by 3-D TCAD in edge-terminated devices is higher than that in 3-D structures obtained from simple width-extended 2-D doping profiles. The use of latter devices, thus, simplifies the 3-D TCAD ${I}$ – ${V}$ analysis and provides a safe margin for ${I} _{\text {HOLD}}$ prediction. The work is relevant for designing the latch-up immunity of ESD protection devices, and it also shows that conventional 2-D TCAD can provide unwanted overestimation of ${I} _{\text {HOLD}}$. [ABSTRACT FROM AUTHOR]

This paper revisits the physics of current filamentation in grounded-gate NMOS (ggNMOS) devices and presents new physical insights which were not addressed in earlier works. A clear distinction between electrical and thermal instabilities is presented. Moreover, filament dynamics under electrical and thermal instability in both silicided and silicide blocked devices is discussed while highlighting observations which contradict with established theory of current ballasting. Interplay between electrical and thermal instabilities and its dependence on the presence or absence of silicide blocking is explored further. Filament spreading in ggNMOS devices and it is dependence on silicide blocking is discussed. Finally, while using the developed physical insights, missing correlation between TLP and HBM extracted failure current of silicided ggNMOS device is explained. [ABSTRACT FROM AUTHOR]

Electrostatic discharge (ESD) robustness improvement of ultra-high-voltage devices is a challenging task. This paper presents an ESD robustness enhancement study of an 800 V junction field-effect transistor (JFET) including a silicon-controlled rectifier (SCR) structure. During a human body model (HBM) event, the fabricated SCR-JFET showed a deep voltage snapback and an unexpectedly high current peak, resulting in an ESD failure due to current filamentation. 3-D TCAD analysis is effectively utilized for ESD enhancement study. First, 3-D HBM simulation reproduces the current filamentation phenomenon and the observed ESD failure. Then, a drain modified SCR-JFET, which includes a p+ ballast region, is studied. TCAD simulations demonstrate ESD robustness improvement with the ballast device and make clear its performance enhancement mechanism. Based on the TCAD study results, the ballast device is fabricated. Photo-emission microscope measurement results clearly show an alleviation of the current filamentation. As a result of HBM tests, we successfully improve HBM robustness from 1.93 kV to 2.63 kV with the ballast structure. [ABSTRACT FROM PUBLISHER]

In this paper the Electrostatic Discharge (ESD) capability of 200 V Fast Recovery Epitaxial Diodes (FREDs) is analysed by means of suitable experiments, TCAD simulations and theoretical analyses. Different doping profiles are investigated in order to improve the ESD robustness of a standard device and an optimized doping profile is proposed. The newly fabricated devices show a remarkably high ESD capability without any significative loss in forward voltage drop and a reduction of the breakdown voltage that does not affect device rating. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the effect of collector design on the onset and the extension of the negative differential resistance (NDR) region that develops in the blocking curves of field-stop (FS) and punch-through (PT) insulated gate bipolar transistors. Differences on the NDR extension and on its temperature behavior for the PT structures with respect to the FS ones are found, and their dependence from the collector design is explained. Subsequently, the dynamic filamentary current conduction mechanism is studied by means of 2-D electrothermal simulations on a wide area structure with many elementary cells on PT and FS devices. The differences between the two structures in terms of filament movement and its influence on the max temperature of the hot spot are then demonstrated to adversely affect the ruggedness of PT devices compared with the FS ones. [ABSTRACT FROM AUTHOR]

In order to reveal cause–effect relationship between collector-side electric field strength ( E collector ) and onset of current filaments under short circuit, a 3.3 kV trench IGBT was investigated by TCAD simulation. It is shown that during short circuit turn-on, current filamentation is triggered by avalanche generation at the collector side, due to high E collector that aroused from low hole injection. During the short circuit turn-off, filaments are induced by avalanche at emitter side. As a consequence, E collector increases in the cell exhibiting current filamentation. The paper also proposes a thorough analysis of the evolution of the filaments in time. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the avalanche behavior of field-stop insulated gate bipolar transistors (IGBTs) by means of analytical and theoretical considerations, supported by ad hoc numerical simulations. A physical explanation of the presence of negative differential resistance branches in the avalanche I-V curve of the IGBT is presented and design criteria are derived to reduce and eventually eliminate this effect. [ABSTRACT FROM PUBLISHER]

Due to the negative-differential-resistance-related instability, the current-density distribution in sufficiently wide devices exhibiting S-shaped I– V characteristics becomes inherently inhomogeneous along the device width. High-current-density on-state (i.e., a current filament) and low-current-density off-state regions are spontaneously formed, leading to the formation of a vertical branch in the I– V curve at a so-called coexistence voltage uCO. In electrostatic discharge (ESD) protection devices (PDs), this vertical I–V branch usually determines the lowest voltage point that can be accessed by a conventional transmission line pulser (TLP). However, the real holding point of device VH, which is related to an I– V part with a homogeneous current distribution, lies below uCO, i.e., VH < uCO. Here, we present a method on how to determine VH and the I– V branch below uCO, which is “hidden” when using a conventional TLP analysis. We use a multilevel TLP system and demonstrate it on a 90-nm technology silicon-controlled rectifier ESD PD. Measurement considerations, which take into account the finite speed of the on-state spreading effect and the self-heating effect, are discussed. Implications relevant for latch-up prevention and for the comparison of experiments with 2-D and 3-D technology computer-aided design simulations are also given. [ABSTRACT FROM AUTHOR]

Time evolution of self-heating and current filamentation are discussed in this paper for shallow-trench-isolation (STI)-type drained-enhanced n-channel metal–oxide–semiconductor (DeNMOS) devices. A deeper insight toward regenerative n-p-n action and its impact over various phases of filamentation and the final thermal runaway is presented. A modified STI-type DeNMOS device is proposed in order to achieve an improvement (\sim\!\!\2 \times) in the failure threshold (IT2) and electrostatic discharge (ESD) window (VT2). The performance and filament behavior of the standard device under charge-device-model-like ESD conditions is also presented, which is further compared with the proposed modified device. [ABSTRACT FROM PUBLISHER]

We present experimental and simulation studies of shallow trench isolation (STI)-type drain-extended n-channel metal–oxide–semiconductor devices under human body model (HBM)-like electrostatic discharge (ESD) conditions. Physical insight toward pulse-to-pulse instability is given. Both the current (ITLP) and time evolution of various events such as junction breakdown, parasitic bipolar triggering, and the base push-out effect are discussed in detail. Differences between the 2-D and 3-D simulation (modeling) approaches are presented, and the importance of 3-D technology-computer-aided-design-based modeling is discussed. Furthermore, a deeper physical insight toward the base push-out is given, which shows significant power dissipation due of space charge build-up, which is found at the onset of self-heating in the 2-D plane. [ABSTRACT FROM PUBLISHER]

A breakdown phenomenon is studied in thin carbon doped GaN layers (GaN:C; carbon concentration 1019 cm−3) embedded between a top metal electrode and bottom n‐doped GaN (n‐GaN). When slowly sweeping positive bias V at the top electrode up and down, a hysteresis is found with transitions to on‐ and off‐states at voltages Vbd,up and Vbd,down (

Current filamentation observed in dc gas discharges is explained considering a self-organization process, the result of which is a nearly spherical double layer known as anode spot. Accelerating electrons at energies sufficient to produce ionizations, the double layer acts as an internal source of charged particles. The striated column, working as current filament, appears after the double layer ‘multiplication.’ The balance between the repulsive electric forces and the attractive magnetic forces acting between striated columns explains the ordered distribution of the current filaments at the anode surface. [ABSTRACT FROM AUTHOR]