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The utilization of SPI-Flash in embedded systems is widespread, primarily serving as program storage during the boot process. As a result, the boot process is influenced to some extent by the SPI-Flash controller. This paper presents a lightweight SPI-Flash controller that simplifies the boot process design by establishing a direct connection between the SPI-Flash and AHB-lite bus interface, enabling rapid program execution in RAM instead of directly from the SPI-Flash. Additionally, the controller can function as a bare-metal program downloader for testing the boot process functionality during FPGA-based SoC (system-on-chip) prototype verification. The system-level simulation and FPGA verification results demonstrate that the proposed SPI-Flash controller successfully achieves its intended functional impact in operations to target the Micron N25Q256A SPI-Flash chip, boot process design, and bare-metal program download. The synthesis results under the SMIC 180 nm 1P8M technology process indicate that this SPI-Flash controller exhibits remarkable performance, power consumption, and area utilization. The source code of the proposed lightweight SPI-Flash controller has been uploaded to GitHub as an open-source project. [ABSTRACT FROM AUTHOR]

The utilization of SPI-Flash in embedded systems is widespread, primarily serving as program storage during the boot process. As a result, the boot process is influenced to some extent by the SPI-Flash controller. This paper presents a lightweight SPI-Flash controller that simplifies the boot process design by establishing a direct connection between the SPI-Flash and AHB-lite bus interface, enabling rapid program execution in RAM instead of directly from the SPI-Flash. Additionally, the controller can function as a bare-metal program downloader for testing the boot process functionality during FPGA-based SoC (system-on-chip) prototype verification. The system-level simulation and FPGA verification results demonstrate that the proposed SPI-Flash controller successfully achieves its intended functional impact in operations to target the Micron N25Q256A SPI-Flash chip, boot process design, and bare-metal program download. The synthesis results under the SMIC 180 nm 1P8M technology process indicate that this SPI-Flash controller exhibits remarkable performance, power consumption, and area utilization. The source code of the proposed lightweight SPI-Flash controller has been uploaded to GitHub as an open-source project.

Aiming at the problem that the traditional SATA controller has a single interface and cannot give full play to the performance of the SSD, a multi-channel high-speed storage circuit based on PCIE to SATA is designed. This design makes full use of the high-bandwidth and low-latency characteristics of the PCIE bus and follows the AHCI protocol, which can greatly reduce the useless seek times and data search time of the hard disk, and improve the read performance. At the same time, the design can support 4 SATA channels and has good scalability. This design combines the characteristics of PCIE and SATA protocols, introduces the system architecture of PCIE to SATA high-speed storage circuit, and elaborates the data stream transmission process based on AHCI protocol. Finally, the circuit is tested based on the FPGA prototype verification. The single-disk read and write rates of the circuit are 562MB/s and 527MB/s, respectively. Compared with the traditional SATA controller, the read and write performance is greatly improved. The test results show that the designed PCIE to SATA high-speed storage circuit has excellent read and write performance, and has good stability and scalability.

Forward error correction (FEC) performance down to 10−15 bit error rate (BER) of a concatenated staircase and Hamming code (CSHC), which was recently proposed for the first 400G inter-data center interconnect standard, is verified with a 50-piece field-programmable gate array (FPGA) implementation at a record 200-Gb/s throughput. The effect of digital noise tail accuracy on the FEC emulation results is investigated. A converging criterion is proposed and demonstrated for achieving high confidence in artificial digital-noise-source-based FPGA emulations. The CSHC performance as a function of decoding iterations of the outer staircase code is investigated, and emulation results show that six staircase decoding iterations is the optimal choice. The FPGA emulations also reveal the existence of an error flare of the CSHC at 10−10 BER, which corrects the predicted BER threshold from 1.25 × 10−2 to 1.21 × 10−2. Further investigations on the effects of interleaving processes and staircase decoding buffer size show that the error flare behavior of the CSHC depends on the decoding buffer size of the outer staircase code. To remove the CSHC error flare, a proper choice of the staircase decoding buffer size is shown to be 6, which also moves the FEC threshold to 1.27 × 10−2. [ABSTRACT FROM AUTHOR]

This paper proposes the architecture of the hash accelerator, developed in the framework of the European Processor Initiative. The proposed circuit supports all the SHA2 and SHA-3 operative modes and is to be one of the hardware cryptographic accelerators within the crypto-tile of the European Processor Initiative. The accelerator has been verified on a Stratix IV FPGA and then synthesised on the Artisan 7 nanometres TSMC silicon technology, obtaining throughputs higher than 50 Gbps for the SHA2 and 230 Gbps for the SHA-3, with complexity ranging from 15 to about 30 kGE and estimated power dissipation of about 13 (SHA2) to 26 (SHA-3) mW (supply voltage 0.75 V). The proposed design demonstrates absolute performances beyond the state-of-the-art and efficiency aligned with it. One of the main contributions is that this is the first SHA-2 SHA-3 accelerator synthesised on such advanced technology. [ABSTRACT FROM AUTHOR]