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The reliability and durability of integrated circuits (ICs), present in almost every electronic system, from consumer electronics to the automotive or aerospace industries, have been and will continue to be critical concerns for IC chip makers, especially in scaled nanometer technologies. In this context, ICs are expected to deliver optimal performance and reliability throughout their projected lifetime. However, real-time reliability assessment and remaining lifetime projections during in-field IC operation remain unknown due to the absence of trustworthy on-chip reliability monitors. The integration of such on-chip monitors has recently gained significant importance because they can provide real-time IC reliability extraction by exploiting the fundamental physics of two of the major reliability degradation phenomena: bias temperature instability (BTI) and hot carrier degradation (HCD). In this work, we present an extensive study of ring oscillator (RO)-based degradation and annealing monitors designed on our latest 28 nm versatile array chip. This test vehicle, along with a dedicated test setup, enabled the reliable statistical characterization of BTI- and HCD-stressed as well as annealed RO monitor circuits. The versatility of the test vehicle presented in this work permits the execution of accelerated degradation tests together with annealing experiments conducted on RO-based reliability monitor circuits. From these experiments, we have constructed precise annealing maps that provide detailed insights into the annealing behavior of our monitors as a function of temperature and time, ultimately revealing the usage history of the IC. [ABSTRACT FROM AUTHOR]

With the technological scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) and the scarcity of circuit design margins, the characteristics of device reliability have garnered widespread attention. Traditional single-mode reliability mechanisms and modeling are less sufficient to meet the demands of resilient circuit designs. Mixed-mode reliability mechanisms and modeling have become a focal point of future designs for reliability. This paper reviews the mechanisms and compact aging models of mixed-mode reliability. The mechanism and modeling method of mixed-mode reliability are discussed, including hot carrier degradation (HCD) with self-heating effect, mixed-mode aging of HCD and Bias Temperature Instability (BTI), off-state degradation (OSD), on-state time-dependent dielectric breakdown (TDDB), and metal electromigration (EM). The impact of alternating HCD-BTI stress conditions is also discussed. The results indicate that single-mode reliability analysis is insufficient for predicting the lifetime of advanced technology and circuits and provides guidance for future mixed-mode reliability analysis and modeling. [ABSTRACT FROM AUTHOR]

The reliability and durability of integrated circuits (ICs), present in almost every electronic system, from consumer electronics to the automotive or aerospace industries, have been and will continue to be critical concerns for IC chip makers, especially in scaled nanometer technologies. In this context, ICs are expected to deliver optimal performance and reliability throughout their projected lifetime. However, real-time reliability assessment and remaining lifetime projections during in-field IC operation remain unknown due to the absence of trustworthy on-chip reliability monitors. The integration of such on-chip monitors has recently gained significant importance because they can provide real-time IC reliability extraction by exploiting the fundamental physics of two of the major reliability degradation phenomena: bias temperature instability (BTI) and hot carrier degradation (HCD). In this work, we present an extensive study of ring oscillator (RO)-based degradation and annealing monitors designed on our latest 28 nm versatile array chip. This test vehicle, along with a dedicated test setup, enabled the reliable statistical characterization of BTI- and HCD-stressed as well as annealed RO monitor circuits. The versatility of the test vehicle presented in this work permits the execution of accelerated degradation tests together with annealing experiments conducted on RO-based reliability monitor circuits. From these experiments, we have constructed precise annealing maps that provide detailed insights into the annealing behavior of our monitors as a function of temperature and time, ultimately revealing the usage history of the IC.

A coupling mechanism between flicker noise and hot carrier degradation (HCD) is revealed in this work. Predicting the flicker noise properties of fresh and aged devices is becoming essential for circuit designs, requiring an understanding of the fundamental noise behaviors. While certain models for fresh devices have been proposed, those for aged devices have not been reported yet because of the lack of a clear mechanism. The flicker noise of aged FinFETs is characterized based on the measure-stress-measure (MSM) method and analyzed from the device physics. It is found that both the mean and deviations of the noise power spectral density increase compared with the fresh counterparts. A coupling mechanism is proposed to explain the trap time constants, leading to the trap characterizations in their energy profiles. The amplitude and number of contributing traps are also changing and are dependent on the mode of HCD and determined by the position of the induced traps. A microscopic picture is developed from the perspective of trap coupling, reproducing well the measured noise of advanced nanoscale FinFETs. The finding is important for accurate flicker noise calculations and aging-aware circuit designs. [ABSTRACT FROM AUTHOR]

In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs). It is found that increasing GIDL bias from 3 V to 4 V achieves a 114.7% VT recovery ratio from HCD. This over-repair phenomenon of HCD by UFM GIDL is deeply discussed through oxide trap behaviors. When the applied gate-to-drain GIDL bias reaches 4 V, a significant electron trapping and interface trap generation of the fresh device with GIDL repair is observed, which greatly contributes to the approximate 114.7% over-repair VT ratio of the device under worst HCD stress (−2.0 V, 200 s). Based on the TCAD simulation results, the increase in the vertical electric field on the surface of the channel oxide layer is the direct cause of an extraordinary electron trapping effect accompanied by the over-repair phenomenon. Under a high positive electric field, a part of channel electrons is captured by oxide traps in the gate dielectric, leading to further VT recovery. Through the discharge-based multi-pulse (DMP) technique, the energy distribution of oxide traps after GIDL recovery is obtained. It is found that over-repair results in a 34% increment in oxide traps around the conduction energy band (Ec) of silicon, which corresponds to a higher stabilized VT shift under multi-cycle HCD-GIDL tests. The results provide a trap-based understanding of the transistor repairing technique, which could provide guidance for the reliable long-term operation of ICs. [ABSTRACT FROM AUTHOR]

With the technological scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) and the scarcity of circuit design margins, the characteristics of device reliability have garnered widespread attention. Traditional single-mode reliability mechanisms and modeling are less sufficient to meet the demands of resilient circuit designs. Mixed-mode reliability mechanisms and modeling have become a focal point of future designs for reliability. This paper reviews the mechanisms and compact aging models of mixed-mode reliability. The mechanism and modeling method of mixed-mode reliability are discussed, including hot carrier degradation (HCD) with self-heating effect, mixed-mode aging of HCD and Bias Temperature Instability (BTI), off-state degradation (OSD), on-state time-dependent dielectric breakdown (TDDB), and metal electromigration (EM). The impact of alternating HCD-BTI stress conditions is also discussed. The results indicate that single-mode reliability analysis is insufficient for predicting the lifetime of advanced technology and circuits and provides guidance for future mixed-mode reliability analysis and modeling.

In this paper, models of hot carrier degradation (HCD) in nMOSFET and nFinFET, combined with the physical mechanism and reaction-diffusion framework and considering saturation effect, are proposed. The HCD data of different technology nodes of nMOSFET and nFinFET are used to verify the accuracy of the models. The results show that the prediction errors of device parameter degradation under different stress voltages are less than 10% for several types of short channel devices, which is better than the existing reported research results. Furthermore, the models have simple analytical expressions that allow them to not only be applied to device HCD prediction, but also be extended to circuit level HCD prediction tool more easily. [ABSTRACT FROM AUTHOR]

A coupling mechanism between flicker noise and hot carrier degradation (HCD) is revealed in this work. Predicting the flicker noise properties of fresh and aged devices is becoming essential for circuit designs, requiring an understanding of the fundamental noise behaviors. While certain models for fresh devices have been proposed, those for aged devices have not been reported yet because of the lack of a clear mechanism. The flicker noise of aged FinFETs is characterized based on the measure-stress-measure (MSM) method and analyzed from the device physics. It is found that both the mean and deviations of the noise power spectral density increase compared with the fresh counterparts. A coupling mechanism is proposed to explain the trap time constants, leading to the trap characterizations in their energy profiles. The amplitude and number of contributing traps are also changing and are dependent on the mode of HCD and determined by the position of the induced traps. A microscopic picture is developed from the perspective of trap coupling, reproducing well the measured noise of advanced nanoscale FinFETs. The finding is important for accurate flicker noise calculations and aging-aware circuit designs.

In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs). It is found that increasing GIDL bias from 3 V to 4 V achieves a 114.7% VT recovery ratio from HCD. This over-repair phenomenon of HCD by UFM GIDL is deeply discussed through oxide trap behaviors. When the applied gate-to-drain GIDL bias reaches 4 V, a significant electron trapping and interface trap generation of the fresh device with GIDL repair is observed, which greatly contributes to the approximate 114.7% over-repair VT ratio of the device under worst HCD stress (−2.0 V, 200 s). Based on the TCAD simulation results, the increase in the vertical electric field on the surface of the channel oxide layer is the direct cause of an extraordinary electron trapping effect accompanied by the over-repair phenomenon. Under a high positive electric field, a part of channel electrons is captured by oxide traps in the gate dielectric, leading to further VT recovery. Through the discharge-based multi-pulse (DMP) technique, the energy distribution of oxide traps after GIDL recovery is obtained. It is found that over-repair results in a 34% increment in oxide traps around the conduction energy band (Ec) of silicon, which corresponds to a higher stabilized VT shift under multi-cycle HCD-GIDL tests. The results provide a trap-based understanding of the transistor repairing technique, which could provide guidance for the reliable long-term operation of ICs.

This paper presents an extensive experimental analysis of hot carrier degradation (HCD) due to DC and large-signal RF stress on a power amplifier (PA) cell in the sub-7GHz frequency band. The reported PA cell is fabricated in a 45-nm RFSOI technology and consists of a single n-channel floating body partially depleted SOI FET. The impact of HCD on the class, conduction angle ($\theta $), and performance of the PA cell is analyzed under DC and large-signal RF stress conditions. Generation of defects and their types, i.e., whether oxide or interface traps, are understood using a combination of RF and DC stress conditions. Our detailed analysis distinguishes HCD mechanisms dominated by oxide and interface traps by studying time slope exponents, changes in the subthreshold swing, threshold voltage, and peak transconductance. The impact of RF stress on the PA cell lifetime is also extracted using a semiempirical model. [ABSTRACT FROM AUTHOR]

Recently, back-end-of-line (BEOL) compatible indium oxide (In2O3) thin-film transistors (TFTs), grown by atomic layer deposition (ALD) with channel thickness of ~1 nm and channel length down to 40 nm, have achieved a record high drain current of 2.2 A/mm at ${V}_{\textit {DS}}$ of 0.7 V. A systematic characterization of the reliability issues, such as positive bias temperature stress (PBTS) and hot carrier degradation (HCD), would allow its immediate integration into innovative ICs, such as 3D-stacked SRAM or on-chip bridge for mixed-voltage systems. Surprisingly, PBTS and HCD are both characterized by a universal two-stage threshold voltage shift ($\Delta \!{V}_{\textit {th}}$ , a positive shift followed by a temperature-activated negative shift). This is attributed respectively to electron trapping/trap-generation and hydrogen-assisted formation of donor-traps. These competing mechanisms of $\Delta ~{V}_{\textit {th}}$ depend on the stress voltages and stress temperature. Unlike traditional logic transistors, HCD in BEOL-TFTs is strongly correlated to PBTS, caused by the much stronger vertical field in an ultra-thin device. Overall, this high-performance BEOL-transistor is remarkably reliable, with a relatively small $\Delta ~{V}_{\textit {th}}$ under PBTS/HCD stress conditions at room temperature (RT). However, self- and mutual heating of BEOL interconnect levels and the resultant threshold voltage variability must be mitigated/managed for its successful integration in various neuromorphic circuits. [ABSTRACT FROM AUTHOR]

It is well-known that regardless of the voltage/temperature/device structure, the hot carrier degradation (HCD) of classical logic transistors scales onto a single universal curve, offering a theory-agnostic approach to predict long-term degradation based on short-term accelerated tests. Based on the experimental results, it has been suggested that the HCD in power transistors [e.g., laterally diffused MOS (LDMOS)] is structurally and functionally so fundamentally different that an analogous universal scaling cannot apply. This article uses a tandem FET (two MOS) model of an LDMOS to explore the physical origin of the anomalous HCD degradation in power transistors and establish the general principle needed to restore the universality of the degradation kinetics. Interestingly, the empirical models used to evaluate HCD degradation in power transistors emerge naturally as approximations of the generalized approach. This article establishes the fact that the physics of HCD is universal and provides an example of nonclassical but predictive degradation in power transistors. This takes us a step closer to a generalized HCD model encompassing all the devices, including logic, memory, and power transistors. [ABSTRACT FROM AUTHOR]

Hot-carrier degradation (HCD) is investigated in silicon trench MOSFETs with field plate compensation. With the aid of charge pumping (CP), it is possible to obtain the total trap densities created by the hot-carrier stress. We will demonstrate that, in combination with TCAD simulations, profiling of the spatial distribution of the damage at the interface is possible in the accessible regions by extending the well-known reverse-bias CP method for planar devices to trench devices. Four process variations are investigated to show the impact of the cell geometry on the degradation location with the results being confirmed by capacitance measurements. It is found that the impact ionization rate seen in drift-diffusion TCAD simulations provides a straightforward means to estimate the defect locations. [ABSTRACT FROM AUTHOR]

In 10-nm node core FinFETs, we analyzed the cause of higher hot carrier degradation (HCD) in pFinFETs than in nFinFETs. Self-heating effect is severe in pFinFETs because SiGe is used as the source/drain materials, which makes the device temperature higher than nFinFETs. Theoretically, because the lifetime of multiple particle (MP) mechanism decreases as temperature increases, degradation due to MP decreases. Therefore, it is difficult for the pure HCD mechanisms to occur more in pFinFETs, which has higher temperature than nFinFETs. However, in pFinFETs, unlike nFinFETs, interface traps can be generated due to negative-bias temperature instability (NBTI) that occurs by the reaction between inversion holes and electrons of Si–H bonds. Also, since NBTI deteriorates more as the temperature increases, the phenomenon of higher degradation in pFinFET than nFinFET can be explained with the NBTI mechanism. Therefore, we propose an additional NBTI mechanism that is caused by high device temperature in pFinFETs even in the HCD condition. In addition, the main components were investigated through measurements of current degradation rate in various voltage conditions, and it was found that NBTI is dominant in pFinFETs. Finally, NBTI that can occur in the HCD condition was predicted through technology computer-aided design (TCAD) simulation. As a result, degradation due to pure hot carriers without NBTI occurs more in nFinFETs than in pFinFETs. [ABSTRACT FROM AUTHOR]

The temperature dependence of defect generation due to hot-carrier stress (HCS) is investigated in long-channel nMOSFETs with a SiO2 insulator. In order to improve the understanding of hot-carrier degradation, we systematically investigate the impact of temperature on the HCS-induced trap densities and their energetic profiles using standard and spectroscopic charge pumping (CP). With the aid of polyheaters, which can rapidly change the device temperature, recovery of the degradation at higher temperatures is minimized by quickly switching the temperature to the characterization temperature of −60 °C. In order to be able to quantitatively analyze the trap profiles measured with spectroscopic CP, a method for finding the correct capture cross section is suggested. Both CP methods yield comparable results, and it is shown that the same types of defects are created at all temperatures. In agreement with the literature, lower stress temperatures during HCS result in the creation of a larger number of defects for our long-channel devices. [ABSTRACT FROM AUTHOR]

As fast charging being a comprehensive application in universal serial bus (USB) type-C products, the high-power delivery may cause the USB type-C interface in the high risk of surge events. Therefore, a switch realized by high voltage N-type metal oxide semiconductor transistor (HVNMOS) has been added to the configuration channel (CC) pin to prevent the internal circuits from surge damage. However, hot carrier degradation (HCD) on the HVNMOS was induced by surge events, especially when the HVNMOS was operating in the ON-state. To mitigate HCD on the HVNMOS switch during surge events, a new over-voltage protection (OVP) design with selected voltage-level detection was proposed and verified in a 0.15-μm BCD technology. The proposed OVP circuit with a positive feedback is designed to turn off the gate of the HVNMOS switch for a longer time when surge zapping on the CC pin. The experimental results from silicon chip have successfully verified the proposed OVP structure in device level and circuit level, respectively. [ABSTRACT FROM AUTHOR]

As foreseen by Keyes in the late 1960s, the self-heating effect has emerged as an important concern for device performance, output power density, run-time variability, and reliability of modern field-effect transistors. The self-heating effect is aggravated as the device footprint scales down for higher level of integration (low-power devices) or as the devices are operated in ultrahigh voltage regimes (high-power devices). In this article, we focus on the implications of self-heating on hot carrier degradation (HCD) of modern transistors by integrating within a coherent theoretical framework a broad range of experimental data scattered in the literature. We explain why system integration exacerbates transistor self-heating, while high-frequency digital operation ameliorates it, suggesting an opportunity for co-optimization. We conclude this article by discussing the various material–device–system design strategies to reduce HCD and suggesting open problems for further research. [ABSTRACT FROM AUTHOR]

A SPICE compatible compact modeling framework is proposed for the time kinetics of threshold voltage shift ($\Delta {V}_{T}$) in FinFETs subjected to hot carrier degradation (HCD) stress. The model is valid for the entire drain (${V}_{D}$) and gate (${V}_{G}$) voltage space and calculates the generation of interface traps for pure HCD ($\Delta {V}_{\text {IT-HC}}$) and for negative bias temperature instability (NBTI) ($\Delta {V}_{\text {IT-BT}}$), hole trapping ($\Delta {V}_{\text {HT}}$), and electron trapping ($\Delta {V}_{\text {ET}}$) as necessary, and considers the self-heating effect (SHE). The model is validated by using ultrafast (10- $\mu \text{s}$ delay) measured data from replacement metal gate (RMG) silicon germanium (SiGe) p-FinFETs having a different fin length (FL) and different nitrogen (N%) in the gate insulator stack. A calibrated TCAD framework is used to verify the impact of pure NBTI for varying ${V}_{G}$ and ${V}_{D}$ stress in the presence of SHE but no HCD. [ABSTRACT FROM AUTHOR]

Comprehensive review and reanalysis are done on previously reported experimental hot carrier degradation data in various MOSFET architectures. The universality of time kinetics and voltage acceleration of degradation, obtained using multiple measurement techniques, is analyzed for OFF- and different ON-state modes in long and short channel planar and drain extended MOSFETs and FinFETs. The similarities and differences of such diverse measurement methods are analyzed. Existing theories are qualitatively benchmarked against this analysis, and capabilities as well as inconsistencies of those theories are discussed. [ABSTRACT FROM AUTHOR]

LDMOS (laterally-diffused-metal-oxide-semiconductor) technology has been studied rigorously for high power and high voltage applications in communication systems, wireless networks, and high-frequency circuits, etc. due to its high voltage handling capability, high power density, low on-resistance, high linearity, etc. Often the device has to face radiation hazards for applications eg. space shuttles, drones, etc. Power transistors face hot carrier degradation (HCD) with total ionizing dose (TID) radiation and the overall performance of the device is degraded with radiation. Reducing or eliminating HCD from an LDMOS needs device structure modification which is often challenging and costly. There is a strong correlation between HCD and TID when coexist. It is important to study the LDMOS under radiation, especially for analog circuit performance parameters. In this work, the laterally defused LDMOS is extensively studied with a Sentaurus device simulator, for circuit application parameters such as threshold voltage (V T H), transconductance (G M), cut-off frequency (f T), output resistance (R 0) , and parasitic capacitances under total ionizing dose (TID) radiation. The device is also studied for low-frequency (1 / f) noise under radiation. The simulation is well-calibrated with experimental results. As experimentally verified earlier, in this device TID can essentially upsurge the overall HCD-limited lifetime of an LDMOS transistor unexpectedly. In addition to better HCD behavior, the device offers better analog performance parameters and 1 / f noise performances under TID radiation. • LDMOS offers better HCD behavior. • LDMOS is sensitive to 1/ f noise power density under gamma radiation. • Guideline for optimized performances and reliability under TID and 1/f noise. [ABSTRACT FROM AUTHOR]

In this letter, the impact of self-heating effect (SHE) on hot carrier degradation (HCD) in multiple-fin silicon-on-insulator (SOI) FinFETs was investigated. First, the ac conductance method has been utilized to extract the thermal resistance ( \textR\mathrm {th} ) of SOI FinFETs with different fin numbers. Then, both dc and ac stresses are applied on the gate and drain of transistors with the source grounded to characterize the HCD. It is found that the device with large fin number demonstrates high-temperature rise caused by SHE, which results in the enhanced generation of oxide bulk trapped charges. Thus, the SHE aggravates the HCD significantly. The influence of SHE on HCD is mitigated when the frequency of ac stress is above 10 MHz. Therefore, special attention to the SHE on HCD must be paid for accurate HCD prediction in FinFETs. [ABSTRACT FROM AUTHOR]