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This paper reports the structural, optical, and electrical properties of dysprosium oxide (Dy2O3) deposited by electron beam deposition under ultra-vacuum on porous p-type GaAs. A porous GaAs layer was produced by electrochemical anodic etching of a (100)-heavily doped p-type GaAs substrate in hydrofluoric acid (HF) and ethanol C2H5OH solution. The surface topography of the elaborated Dy2O3 layer was determined based on atomic force microscopy (AFM) images. AFM studies showed that the structure and roughness of the Dy2O3 layer were strongly dependent on the roughness and surface of porous GaAs. Dy2O3 is polycrystalline and exhibits a cubic crystalline structure, as confirmed by x-ray diffraction (XRD) analysis. The optical properties of Dy2O3/p-porous GaAs were analyzed using various techniques including ellipsometry and photoluminescence (PL) to obtain information on surface and interface quality, bandgap, optical constants, dielectric constant, and thickness. The photoluminescence (PL) spectra revealed an intense peak at 835 nm and additional weak emission peaks at 473 nm and 540 nm, respectively. The observed intense peak can be directly attributed to the interband recombination process of free carriers in the direct bandgap of p-GaAs, while the weak emission peaks at 473 nm and 540 nm correspond to 4F9/2-6H15/2 and 4F9/2-6H13/2 transitions, respectively. In the spectral region of 350 nm to 500 nm, the average thickness of the Dy2O3 layer was determined to be 11 nm. The electrical properties of the (Co/Au)/Dy2O3/p-porous GaAs metal–oxide–semiconductor (MOS) capacitor were investigated via capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements in the temperature range of 100–400 K and frequency range of 50 Hz to 1 MHz, respectively. The experiments demonstrated that both capacitance and conductance were influenced by temperature and frequency. Additionally, the effect of temperature on interface state density (Nss) was studied, which showed that an increase in temperature led to a decrease in the interface state density (Nss) of the (Co/Au)/Dy2O3/p-porous GaAs (MOS) capacitor, as calculated by the Hill–Coleman method. The mean values of Nss for the (Co/Au)/Dy2O3/p-porous GaAs (MOS) capacitor were determined to be approximately 1012 eV−1 cm−2, making it suitable for electronic device applications. The lower values of Nss can be attributed to a low amount of local defect microstructure at the Dy2O3/p-porous GaAs interface due to the incorporation of the Dy2O3 layer into the porous GaAs. The electrical conductivity of the (Co/Au)/Dy2O3/p-porous GaAs (MOS) capacitor was studied using impedance spectroscopy in the frequency range from 50 Hz to 1 MHz at temperatures ranging from 80 K to 450 K. At low frequencies, the conductivity of alternating current (σAC) remained nearly constant, whereas at high frequencies, it increased rapidly, representing σDC and σAC, respectively. The Arrhenius plot of σAC shows two distinct slopes corresponding to two activation energies, 35 MeV and 10 MeV, in the chosen temperature range. [ABSTRACT FROM AUTHOR]

The energy distribution of the interface states (Nss) and relaxation time (τ) are calculated from the capacitance-frequency (C-f) characteristics for Al/p-type Si/Al metal-semiconductor and Al/V2O5/p-type Si/Al metal–interfacial layer–semiconductor diodes with and without anodic surface passivation. The experimental results show that the density of the interface states and the relaxation times increase almost exponentially with the bias from the top of the valence band to the center of the gap for each diode produced. At the same time, using the C-f characteristics, the dielectric properties such as the dielectric constant (ε′), dielectric loss (ε″), dielectric loss tangent (tanδ), real and imaginary portions of the electric modulus (M' and M″) and ac electrical conductivity (σac) are investigated in this study. The analysis was performed at room temperature, in the frequency range from 1 kHz to 10 MHz, and the voltage range from 0 to 0.24 V. The experimental results show that the ε′, ε″ and tanδ values decrease with increasing frequency while σac, M′ and M″ values increase. This results will show that dielectric parameters are strongly frequency dependent. [ABSTRACT FROM AUTHOR]

Time-dependent second-harmonic generation (TD-SHG) is an emerging sensitive and fast method to qualitatively evaluate the interface quality of the oxide/Si heterostructures, which is closely related to the interfacial electric field. Here, the TD-SHG is used to explore the interface quality of atomic layer deposited HfO2 films on Si substrates. The critical SHG parameters, such as the initial SHG signal and characteristic time constant, are compared with the fixed charge density ( Q o x ) and the interface state density ( D i t ) extracted from the conventional electrical characterization method. It reveals that the initial SHG signal linearly decreases with the increase in Q o x , while D i t is linearly correlated to the characteristic time constant. It verifies that the TD-SHG is a sensitive and fast method, as well as simple and noncontact, for evaluating the interface quality of oxide/Si heterostructures, which may facilitate the in-line semiconductor test. [ABSTRACT FROM AUTHOR]

In this study, the effects of an Al2O3 interfacial layer (IL) on the characteristics of ferroelectric field-effect transistors (FeFETs) with Hf0.5Zr0.5O2 (HZO) gate dielectrics on Si substrates were investigated. FeFETs with HZO gate dielectrics have gained considerable attention owing to their compatibility with modern fabrication processes and scalability. However, during HZO deposition on Si substrates, an ultrathin metal silicate IL with a low dielectric constant is formed in an uncontrolled manner, leading to a significant voltage drop and the generation of interface traps during device operation. To address this issue, an ultrathin Al2O3 IL with a thickness less than 2 nm was introduced between the HZO film and Si substrate via in situ atomic layer deposition. The impact of this IL on a memory window (MW) and endurance characteristics was evaluated by comparing the devices with and without an intentional Al2O3 IL. The obtained results revealed that the Al2O3 IL effectively suppressed the interface trap generation, expanded the MW, and enhanced the transistor endurance characteristics. This described approach can be potentially used for improving the reliability of FeFETs fabricated on Si substrates. [ABSTRACT FROM AUTHOR]

Our study examined how native oxide layers, InN and InSb, affected the current-voltage and capacitance-voltage characteristics of the Au/n-InP Schottky diode at a temperature of 300 K with and without interface states, traps, and tunneling current. The simulation was carried out using the Atlas-Silvaco-Tcad device simulator. From our results, we found that the effective barrier heights were measured to be 0.474 eV, 0.544 eV, and 0.561 eV via I-V measurements and 0.675 eV, 0.817 eV, and 0.80 eV via C-V measurements. Additionally, we utilized the high-low frequency method to calculate the average density of interface state density, which was determined to be approximately 6.03 . 1011 and 3.33 . 1012 сm – 2 . eV – 1. The results indicate that a thin film of InN and InSb can effectively passivate the InP surface, as evidenced by the good performance of the passivized sample. [ABSTRACT FROM AUTHOR]

Oxygen post annealing is a promising method for improving the quality of the SiC metal oxide semiconductor (MOS) interface without the introduction of foreign atoms. In addition, a low oxygen partial pressure annealing atmosphere would prevent the additional oxidation of SiC, inhibiting the generation of new defects. This work focuses on the effect and mechanism of low oxygen partial pressure annealing at different temperatures (900–1250 °C) in the SiO2/SiC stack. N2 was used as a protective gas to achieve the low oxygen partial pressure annealing atmosphere. X-ray photoelectron spectroscopy (XPS) characterization was carried out to confirm that there are no N atoms at or near the interface. Based on the reduction in interface trap density (Dit) and border trap density (Nbt), low oxygen partial pressure annealing is proven to be an effective method in improving the interface quality. Vacuum annealing results and time of flight secondary ion mass spectrometry (ToF-SIMS) results reveal that the oxygen vacancy (V[O]) filling near the interface is the dominant annealing mechanism. The V[O] near the interface is filled more by O2 in the annealing atmosphere with the increase in temperature. [ABSTRACT FROM AUTHOR]

The recently proposed high–low Kelvin probe force microscopy (KPFM) enables evaluation of the effects of semiconductor interface states with high spatial resolution using high and low AC bias frequencies compared with the cutoff frequency of the carrier transfer between the interface and bulk states. Information on the energy spectrum of the interface state density is important for actual semiconductor device evaluation, and there is a need to develop a method for obtaining such physical quantities. Here, we propose high–low Kelvin probe force spectroscopy (high–low KPFS), an electrostatic force spectroscopy method using high- and low-frequency AC bias voltages to measure the interface state density inside semiconductors. We derive an analytical expression for the electrostatic forces between a tip and a semiconductor sample in the accumulation, depletion, and inversion regions, taking into account the charge transfer between the bulk and interface states in semiconductors. We show that the analysis of electrostatic forces in the depletion region at high- and low-frequency AC bias voltages provides information about the interface state density in the semiconductor bandgap. As a preliminary experiment, high-low KPFS measurements were performed on ion-implanted silicon surfaces to confirm the dependence of the electrostatic force on the frequency of the AC bias voltage and obtain the interface state density.

Donor-Acceptor (D-A) polymer field-effect transistors (pFETs) are at the cutting edge of organic electronics. However, some fundamental cognition of interface states remains unquantified, particularly at different dynamic scales. In this study, the interface states of D-A polymer transistors are quantified using the dynamic pumping method. The experimental results indicate that the interface state density of the transistor is insensitive to the measurement pulse condition and stays within the range of $ {10}^{ {12}}\,\,\sim \,\, {10}^{ {13}}\,\,\rm {cm}^{ {-2}}$ . The experiments described in this paper provide a quantitative analysis of interface states. This analysis can serve as effective guidance for optimizing future devices.

In this paper, the effect of atomic layer deposition (ALD)-derived Al2O3 passivation layers and annealing temperatures on the interfacial chemistry and transport properties of sputtering-deposited Er2O3 high-k gate dielectrics on Si substrate has been investigated. X-ray photoelectron spectroscopy (XPS) analyses have showed that the ALD-derived Al2O3 passivation layer remarkably prevents the formation of the low-k hydroxides generated by moisture absorption of the gate oxide and greatly optimizes the gate dielectric properties. Electrical performance measurements of metal oxide semiconductor (MOS) capacitors with different gate stack order have revealed that the lowest leakage current density of 4.57 × 10−9 A/cm2 and the smallest interfacial density of states (Dit) of 2.38 × 1012 cm−2 eV−1 have been achieved in the Al2O3/Er2O3/Si MOS capacitor, which can be attributed to the optimized interface chemistry. Further electrical measurements of annealed Al2O3/Er2O3/Si gate stacks at 450 °C have demonstrated superior dielectric properties with a leakage current density of 1.38 × 10−9 A/cm2. At the same, the leakage current conduction mechanism of MOS devices under various stack structures is systematically investigated. [ABSTRACT FROM AUTHOR]

In this work, to determine the tunneling effect on the performance of silicon heterojunction (SHJ) solar cells, we use AFORS-HET software to systematically study the carrier transport mechanism in different forward bias ranges under dark conditions. We confirm that the carrier transport in the p-type SHJ solar cell is determined by the recombination process at lower voltage (V < 0.3 V) and the tunneling current at higher voltage (0.3 < V < 0.6 V). Our results also suggest that the tunneling affected by the interface state density and doping level of a-Si:H influences the performance of devices. Moreover, we propose a new strategy to improve the performance of SHJ solar cells. By optimizing the above parameters, it was possible to increase the efficiency of a-Si:H(n)/c-Si(p)/a-Si:H(p) and a-Si:H(p)/c-Si(n)/a-Si:H(n) SHJ solar cells to 25.40% and 24.45%, respectively, to reduce the influence of the tunneling effect on the device. This work can be a useful reference for solar cell production and preparation. [ABSTRACT FROM AUTHOR]

The Au/SnO2/n-InP heterojunction (HJ) diode was fabricated with an e-beam deposited tin oxide (SnO2) film in between the Au and InP substrate as an interlayer and explored its current–voltage characteristics in the temperature range of 200–400 K. The zero-bias barrier height (ΦB0) and ideality factor (n) values determined for HJ diode changed from 0.51 eV and 4.32 at 200 K to 0.81 eV and 1.63 at 400 K, respectively. The ΦB0 increases, while n decreases with increasing the temperature which may be the evidence of the barrier height inhomogeneities at the interface. The deeds of nkT/q versus kT/q plot for HJ diode specified that a combination of thermionic field emission and field emission mechanisms, i.e. the tunnelling mechanism, may be ruled especially at low temperatures. The plots ΦB0 versus n, ΦB0−q/2kT and (n−1 − 1) − q/kT show linearity, which may be due to the existence of a Gaussian distribution of the barrier height. From Φap versus q/2kT plot, the mean barrier ( Φ B 0 ¯ ) and standard deviation (σ0) are estimated as 1.1149 eV and 0.1473 V, respectively. Further, the estimated interface state density (NSS) for HJ diode decreases with increasing temperature such behaviour is ascribed to molecular restructuring and reordering at the interface with the impact of temperature. At all temperatures, it is noted that the reverse leakage current is ruled by the Poole–Frenkel emission at the low voltage region whereas Schottky emission is dominated at the high voltage region. [ABSTRACT FROM AUTHOR]

We examined the impact of post-deposition annealing (PDA) on SiO _2 /SiC structures formed by plasma nitridation of the SiC surface followed by sputter deposition of SiO _2 . The interface state density near the conduction band edge of SiC was reduced from about 2 × 10 ^12 to 1 × 10 ^11 eV ^−1 cm ^−2 as the CO _2 -PDA temperature increased from 1050 °C to 1250 °C. In addition, the sample treated by CO _2 -PDA exhibited substantially higher immunity against positive gate bias stress than the standard NO nitridation. Our findings indicate that defect passivation by CO _2 -PDA plays a crucial role in improving the performance and reliability of SiC MOS devices formed by sputter-SiO _2 deposition.

Oxygen post annealing is a promising method for improving the quality of the SiC metal oxide semiconductor (MOS) interface without the introduction of foreign atoms. In addition, a low oxygen partial pressure annealing atmosphere would prevent the additional oxidation of SiC, inhibiting the generation of new defects. This work focuses on the effect and mechanism of low oxygen partial pressure annealing at different temperatures (900–1250 °C) in the SiO2/SiC stack. N2 was used as a protective gas to achieve the low oxygen partial pressure annealing atmosphere. X-ray photoelectron spectroscopy (XPS) characterization was carried out to confirm that there are no N atoms at or near the interface. Based on the reduction in interface trap density (Dit) and border trap density (Nbt), low oxygen partial pressure annealing is proven to be an effective method in improving the interface quality. Vacuum annealing results and time of flight secondary ion mass spectrometry (ToF-SIMS) results reveal that the oxygen vacancy (V[O]) filling near the interface is the dominant annealing mechanism. The V[O] near the interface is filled more by O2 in the annealing atmosphere with the increase in temperature.

This work examines the structural and chemical characteristics of spin-coated magnesium oxide (MgO) on undoped InP (un-InP) and its effects on the barrier parameters and current transport phenomena in the Au/un-InP Schottky contact (SC). Using XRD and XPS, the structural and chemical features of MgO are assessed, confirming that the MgO was deposited on un-InP. The current-voltage (log(I)-V) features were measured for the SC and Au/MgO/un-InP metal/insulator/semiconductor (MIS)-type Schottky contact. The MIS contact revealed an excellent rectification behavior as compared to the SC. The calculated barrier height (Φ b) was higher for the MIS contact (0.61 eV) than the SC (0.52 eV), which implies that the MgO interlayer influences the Φ b of the SC. The Φ b was also estimated using the Cheung's, Mikhelashvili and Norde procedures, the values are similar, indicating their stability and reliability. The acquired interface state density (N SS) of the MIS contact was less than the SC, proving that the MgO interlayer reduced the N SS. The ohmic behavior was observed in the lower bias region for the SC and MIS contacts, while the trap-free space-charge-limited current (SCLC) was noted in the moderate and upper bias regions of the MIS contact under forward bias. Poole-Frenkel emission (PFE) governs at a lower bias, while Schottky emission (SE) dominates at the upper bias of SC and MIS contacts under reverse bias. These findings demonstrate the potential application of MgO interlayer in advancing electronic devices. • Structural and chemical properties of MgO films are explored by XRD and XPS. • Electrical features of Au/un-InP Schottky contact and Au/MgO/un-InP HJ were investigated. • Higher barrier height is acquired for the HJ than the Schottky contact. • Interface state density of HJ is lesser as compared to the Schottky contact. • Current transport process was studied for the Schottky contact and HJ contacts. [ABSTRACT FROM AUTHOR]

In this paper, the effect of atomic layer deposition (ALD)-derived Al2O3 passivation layers and annealing temperatures on the interfacial chemistry and transport properties of sputtering-deposited Er2O3 high-k gate dielectrics on Si substrate has been investigated. X-ray photoelectron spectroscopy (XPS) analyses have showed that the ALD-derived Al2O3 passivation layer remarkably prevents the formation of the low-k hydroxides generated by moisture absorption of the gate oxide and greatly optimizes the gate dielectric properties. Electrical performance measurements of metal oxide semiconductor (MOS) capacitors with different gate stack order have revealed that the lowest leakage current density of 4.57 × 10−9 A/cm2 and the smallest interfacial density of states (Dit) of 2.38 × 1012 cm−2 eV−1 have been achieved in the Al2O3/Er2O3/Si MOS capacitor, which can be attributed to the optimized interface chemistry. Further electrical measurements of annealed Al2O3/Er2O3/Si gate stacks at 450 °C have demonstrated superior dielectric properties with a leakage current density of 1.38 × 10−9 A/cm2. At the same, the leakage current conduction mechanism of MOS devices under various stack structures is systematically investigated.

Indium nitride (InN)-based nanostructures have attracted substantial interest in the development of next-generation nanostructured optoelectronic devices. By expanding the light absorption range, the concept of heterostructures is of paramount significance in optoelectronics. Herein, we report a self-powered photodetector using In2O3/InN core–shell nanorods (NRs). InN NRs were grown using molecular beam epitaxy, and a radial In2O3/InN core–shell NR heterojunction with an In2O3 polycrystalline sheath layer was fabricated using hydrogen plasma treatment. The temperature-dependent current–voltage characteristics exhibit nonideal behavior, and the interface states cause deviation in barrier heights (BHs). The calculated BHs for InN and In2O3/InN core–shell heterostructure are estimated to be 0.47 and 0.62 eV, respectively. The In2O3/InN core–shell heterostructure achieved the highest photosensitivity and detectivity values of 3.22 A/W and 1.07 × 1011 Jones under λ = 465 nm (0.64 mW/cm2), respectively, in the self-power mode. This figure of merit is retained in 382–465 nm spectral regions. The maximum responsivity noticed at 465 nm is believed to be the intermediate oxygen defect energy levels within the forbidden gap of In2O3. The high performance was also attributed to the passivation of the InN NR surfaces by In2O3. The study would be beneficial for the development of solar-blind photodetectors. [ABSTRACT FROM AUTHOR]

We present SiO2/GaN interfaces with a low interface state density and a high breakdown electric field. The SiO2 films were deposited by plasma-enhanced atomic layer deposition (ALD) using bis(diethylamino)silane and O2 plasma at 300 °C on n-type GaN (0001) homoepitaxial layers. An interface state density of less than 1011 cm−2 eV−1 at 0.3 eV below the conduction band edge was confirmed by the conductance method. The value is much lower than those of previously reported ALD-SiO2/GaN interfaces (1012–1013 cm−2 eV−1). A low fixed charge density at the SiO2/GaN interface of 3.7 × 1011 cm−2 and a high dielectric breakdown field of ~10 MV cm–1 were obtained. Moreover, the interface state density and current−voltage characteristics were further improved by post-deposition annealing at 400 °C in N2 ambient. Scanning transmission electron microscopy with energy-dispersive X-ray analysis revealed the existence of a GaO x interlayer between SiO2 and GaN. The unintentionally formed interlayer could be one of the reasons for the improvement of interface properties at ALD-SiO2/GaN. [ABSTRACT FROM AUTHOR]

In this study, a set of the interface state density (ISD) formulae was derived from the Schottky effect. In contrast to the conventional approximation, a new approximation for the ISD formulae gives very unusual values in the case of forward bias or reverse bias. The former ISD formula contains the oxide thickness in the metal–semiconductor interface region, whereas the new approximation formulae do not contain the oxide thickness. They depend on the applied voltage and built-in potential in the case of both bias. Besides, lowering barrier height is called the Schottky effect. A couple of the new ISD formulae can be proportioned to each other. The ratio is a new coefficient. Moreover, the coefficient is inversely proportional with the a cceptor concentration and third power of zero-voltage depletion length. Moreover, that fraction is inversely proportional to the acceptor concentration and cubic power to depletion length. [ABSTRACT FROM AUTHOR]

Threshold voltage (${V}_{\text {TH}}$) hysteresis affects the reliability of silicon carbide (SiC) MOSFETs. To evaluate the ${V}_{\text {TH}}$ hysteresis effect on switching characteristics, this article first investigates the ${V}_{\text {TH}}$ hysteresis in the static characteristics of three SiC MOSFETs with different gate structures. The results illustrate the density of the interface states in different gate structures. Then, the effect of ${V}_{\text {TH}}$ hysteresis on dynamic characteristics under varying OFF-state starting voltages (${V}_{\text {G}}^{ \mathrm{\scriptscriptstyle OFF}}$) is evaluated by experiment. Furthermore, the effect mechanism of ${V}_{\text {TH}}$ hysteresis and ${V}_{\text {G}}^{ \mathrm{\scriptscriptstyle OFF}}$ on switching characteristics is analyzed. Under the effect of the ${V}_{\text {TH}}$ hysteresis, a smaller ${V}_{\text {G}}^{ \mathrm{\scriptscriptstyle OFF}}$ reduces ${V}_{\text {TH}}$ when the device turns on. This phenomenon leads to a reduction in the turn-on delay and consequently lowers the turn-on loss. Therefore, the ${V}_{\text {TH}}$ hysteresis is a significant factor for gate driver design of SiC MOSFETs. [ABSTRACT FROM AUTHOR]

To determine the influence of the thin polymer interface film on the electrical and dielectric characteristics of the Al/p-Si MS structure, the Graphene doped (Bi2Te3–Bi2O3–TeO2): PVP film was deposited on the silicon substrate using the spin-coating method. The mean size of these nanostructures was found less than 50 nm using the XRD method. EDX profile shows that the structure of Bi2Te3–Bi2O3–TeO2 consists of the bismuth (Bi), tellurium (Te), and oxygen (O) atoms and also not consists of other impurities or compounds. The key electrical and dielectric parameters of metal–semiconductor (MS) and metal-polymer/semiconductor nanocomposite structures were examined using I–V and Z–f analyses. The values of saturation-current (I0), barrier-height (BH) at zero-bias (ΦB0), ideality factor (n), series and shunt resistances (Rs, Rsh) data for both structures were derived from the I–V experiments at ± 6 V voltage scales and compared with them. The energy distributions of interface state density (Dit) were also acquired from the voltage-dependent ΦB(V) and n(V) data. Finally, the frequency dependence of complex dielectric (ε* = ε′ − jε″) and electric modulus (M* = M′ + jM″), dielectric loss tangent (tanδ), and ac electrical conductivity (σac) values were evaluated from the C–f and G/ω–f experiments for both structures at 102–106 Hz frequency scale. The results depict that the Bi2Te3–Gr: PVP organic layer improves the quality of the MS structure as it reduces the leakage current, n, and Dit and increases the Rsh, BH, and ε′. [ABSTRACT FROM AUTHOR]

[Display omitted] • Optical and structural properties of ZnPc are studied using UV–Vis and XRD. • Chemical properties of ZnPc are assessed by XPS. • MPS diode demonstrations a good rectifying behavior compared to the MS. • ZnPc interfacial layer increase the effective BH of the MS. • Photodiode properties of MPS are measured. This work explores the effect of zinc phthalocyanine (ZnPc) on the electrical properties of Au/un-InP metal/semiconductor (MS) diode and characterizes its surface topography, structural, chemical and optical properties using AFM, FESEM, XRD, XPS and UV–Vis procedures. XRD and XPS results show that the ZnPc layer was formed onto the InP substrate. The electrical properties of the Au/ZnPc/un-InP metal/polymer/semiconductor (MPS) diode were measured using the current–voltage (I-V) procedure. The results of MPS were compared with the results of the MS. The MPS diode exhibited a higher rectifying nature with reduced reverse leakage current as compared to the MS. Higher barrier height (Φ b) was obtained for the MPS (0.80 eV) than the MS (0.65 eV). The Φ b , n and R S values of the MS and MPS were evaluated using Cheung's and Norde methods. The Φ b values obtained from the J-V, Cheung's and Norde functions were nearly matched with each other, suggesting their consistency and validity. The lower N SS value was acquired for the MPS compared to the MS, indicating a substantial influence of the ZnPc interlayer on the N SS of the MS diode. The photodiode properties of the MPS structure were also measured under dark and illumination wavelengths ranging from 400 nm to 1000 nm. The responsivity and photo-dark-current ratio properties of the ZnPc/InP photodiode indicate the efficacy of the ZnPc layer as an active photo absorber. The findings suggest that the ZnPc layer has potential material for developing next-generation optoelectronic devices. [ABSTRACT FROM AUTHOR]

• (110) ZnO/(100) Nb:SrTiO 3 (NSTO) heterojunction shows bipolar resistive switching. • (110) ZnO/(100) NSTO heterojunction also shows negative differential resistance. • ZnO heterojunctions on (110) and (111) NSTO exhibit typical rectifying behaviors. • ZnO film on (100) NSTO exhibits two orthogonal domains and fourfold symmetry. Zinc oxide (ZnO) films were grown epitaxially on Nb-doped SrTiO 3 (NSTO) substrates with different orientations using laser pulse deposition to create the (11 2 ¯ 0)ZnO/(100)NSTO, (0002)ZnO/(110)NSTO and (0002)ZnO/(111)NSTO heterojunctions. Epitaxial ZnO films on the (100) NSTO had two orthorgonal domains, resembling the fourfold symmetry of the (100) NSTO substrate. This good matching between the grown ZnO film and NSTO substrate resulted in a lower growth rate, smoother and denser surface, and a higher density of interface defect states. The interface state density was approximately 4.4 × 1012 eV−1cm−2, which was notably higher than that of the other two heterojunctions. Electrical transport studies revealed that ZnO/(100)NSTO heterojunction demonstrated bipolar resistive switching and negative differential resistance (NDR) due to a higher density of donor interface states from contributions of oxygen vacancies, while both the ZnO/(110)NSTO and ZnO/(111)NSTO heterojunction exhibited typical rectifying behavior. The preliminary investigation into synaptic behaviors suggested that (11 2 ¯ 0) ZnO/(100)NSTO heterojunction holds significant potential in brain-inspired neuromorphic computing systems. [ABSTRACT FROM AUTHOR]

[Display omitted] • Tm 2 O 3 passivation layer was successfully grown on 4H-SiC substrate. • Concentration of oxygen vacancies were reduced in the annealed passivation layer. • Curbing the existence of Tm-O suboxide in the annealed passivation layer. • Nitrogen ions were successfully incorporated into the Tm 2 O 3 lattice. • MOS characteristics for the Tm 2 O 3 /4H-SiC structure was systematically reported. Thulium oxide (Tm 2 O 3) passivation layer (PL) deposited on 4H-silicon carbide (SiC) that was subjected to postdeposition annealing at 700 °C in forming gas-oxygen-forming gas ambient was reported for the first time in this work. X-ray photoelectron spectroscopy characterization revealed the success of annealing process in minimizing the concentration of oxygen vacancies and also curbed the presence of Tm O suboxide bonding in the annealed Tm 2 O 3 PL. In addition, XPS characterization has also disclosed the incorporation of nitrogen ions into the Tm 2 O 3 lattice through the annealing process in which grazing incidence X-ray diffraction has also revealed the shift of detected peaks with regards to Tm 2 O 3 phases to small diffraction angles. Although X-ray reflectivity measurements have disclosed the formation of thicker SiO 2 interfacial layer (IL) for the annealed Tm 2 O 3 PL, the acquisition of a higher dielectric constant (k) by the annealed PL when compared to as-deposited PL has suggested that the formation of SiO 2 IL has minimal effect toward the k value of annealed PL. Metal-oxide-semiconductor characteristics of the annealed Tm 2 O 3 PL on 4H-SiC was systematically reported in this letter. [ABSTRACT FROM AUTHOR]

The effect of atomic-layer-deposition (ALD)-derived Al2O3 passivation layer on the interface quality of Er2O3/Al2O3/InP laminated stacks and the improvement of electrical performance has been investigated systematically. The chemical bonding states measured by high-resolution X-ray photoelectron spectroscopy (XPS) reveal that the ALD-derived Al2O3 passivation layer can effectively inhibit the diffusion of substrate elements to optimize the interface quality. Electrical characterizations show that the optimized sample has demonstrated improved electrical properties, including the large dielectric constant of 20 and the suppressed leakage current density of 4.10 × 10−7 cm2. In addition, the leakage current conduction mechanisms are also investigated as a function of thickness of Al2O3 passivation layer. The optimized interface state density extracted from the conductance method has reduced from 1.30 × 1012 eV−1cm2 of Er2O3/InP to 7.27 × 1011 eV−1cm2 of Er2O3/Al2O3/InP by adjusting the passivation layer thickness. As a result, it can be also confirmed that the passivation treatment is beneficial to inhibit the element’s diffusion and optimize the interface quality, significantly controlling the capacitor degradation caused by the leakage current through the stacked oxide layer. [ABSTRACT FROM AUTHOR]

The effects of a process that minimizes oxidation of SiC on the channel mobility of heavily doped 4H-SiC (0001), (112Ě„0) and (11Ě„00) metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated. High field-effect mobilities were obtained for these MOSFETs even when the acceptor concentration of the p-body (N A) exceeded 1 Ă— 1018 cmâˆ'3. The field-effect mobility for the (0001) MOSFETs reached 25 cm2 Vâˆ'1 sâˆ'1 (N A = 1 Ă— 1018 cmâˆ'3). The fabricated (11 2 ÂŻ 0) and (1 1 ÂŻ 00) MOSFETs showed very high channel mobilities of 125 cm2 Vâˆ'1 sâˆ'1 (N A = 1 Ă— 1018 cmâˆ'3) and 80 cm2 Vâˆ'1 sâˆ'1 (N A = 5 Ă— 1018 cmâˆ'3), respectively. [ABSTRACT FROM AUTHOR]

A novel post-oxidation annealing (POA) process with supercritical N2O (SCN2O) fluid is reported to be highly effective in improving the interface properties of the SiO2/4H–silicon carbide (SiC) (0001) systems. After SCN2O POA, the interface state density reduces to 2.8 × 1011 eV−1cm−2, which is about 3.5 times lower than that after a traditional high-temperature N2O POA process. Meanwhile, the highest oxide critical electric field shows an increase of 18.19% and the near-interfacial oxide traps is reduced by 69.90% compared with that after N2O POA process. The process temperature is as low as 120 °C. The significantly reduced processing temperature avoids additional defect generation while the supercritical state provides a stronger nitridation effect. SCN2O annealing is a promising candidate for POA process toward high-performance SiC power metal-oxide-semiconductor field effect transistors (MOSFETs). [ABSTRACT FROM AUTHOR]

We fabricated Al2O3/LaAlO3/SiO2 (ALS) gate stacks on 4H-SiC, with LaAlO3 (LAO) film being annealed in O2 atmosphere. The ALS gate stack annealed at 700 °C exhibits a much higher breakdown effective electric field (Eeff), which is approximately 1.8 times higher than that of traditional SiO2 gate oxide. The ALS gate stack also yields a low interface state density (Dit) thanks to the intact LAO film. However, an annealing temperature as high as 800 °C induced traps in the LAO film and deteriorated the SiO2–SiC interface. The 700 °C-annealed LAO film with a high dielectric constant (κ) of 14 and a low trap density, coupled with good electrical characteristics, makes it a promising gate dielectric for SiC power metal-oxide-semiconductor (MOS) device applications. [ABSTRACT FROM AUTHOR]

ZnO films (5 nm and 20 nm) have been grown on GaN single-crystal substrates by thermal atomic layer deposition (ALD) and the electrical properties of n-GaN Schottky contacts modified by such ultrathin ZnO films have been characterized. Compared with 5-nm-thick ZnO, 20-nm-thick ZnO exhibited a better rectifying nature. The average barrier height and ideality factor at room temperature were extracted to be 0.64 eV and 2.33 eV, and 1.01 eV and 1.16 eV, for 5-nm- and 20-nm-thick ZnO, respectively. These results indicate that both the barrier height and ideality factor were altered effectively by changing the ZnO thickness. The temperature-dependent reverse current–voltage (I–V) characteristics revealed that tunneling was dominant for the 5-nm-thick ZnO. A laterally inhomogeneous barrier was appropriate to explain the forward I–V characteristics for both samples. Based on the parallel conductance method and forward I–V data, a lower interface state density was observed for 20-nm-thick ZnO, implying improved interface quality. These results suggest that the electrical properties of n-GaN Schottky contacts could be easily modulated by changing the ZnO thickness. [ABSTRACT FROM AUTHOR]

In this study, three different types of Schottky Barrier diodes were fabricated: Metal-Semiconductor (Au/p-Si) diodes, and pure polyvinyl alcohol (PVA) interface (Au/PVA/p-Si) and 3% Graphene doped PVA interface (Au/PVA:Gr/p-Si) in order to investigate and develop the effect of polymer interface material on the electrical properties of diodes. The electrical properties of the prepared diodes besides the effect of PVA and PVA:Gr interfacial material was investigated. The current-voltage characteristics of each diodes were examined at room temperature. Basic electrical parameters of Au/p-Si, Au/PVA/p-Si, and Au/PVA:Gr/p-Si Schottky Barrier diodes such as series resistance (Rs), barrier height (ΦB0), interface state density (Nss) and ideality factor (n) was obtained from Termionic Emission (TE) theory by using current-voltage data. Norde method was also used to compare the Rs and ΦB0 parameters obtained by the Thermionic Emission theory. The values of n, Rs, and ΦB0 obtained by TE method were found as 14.46, 275.33 Ω, and 0.66 eV for Au/p-Si, 4.98, 155.58 Ω, and 0.72 eV for Au/PVA/p-Si, while it was calculated as 5.61, 432.43 Ω, and 0.77 eV for Au/PVA:Gr/p-Si, respectively. The Rs and ΦB0 values obtained by the Norde method were obtained as 362.39 Ω and 0.70 eV for Au/p-Si, 175.07 Ω and 0.75 eV for Au/PVA/p-Si, while it was found as 525.21 Ω and 0.76 eV for Au/PVA:Gr/p-Si. Values found with Norde and Termionic Emission methods are compatible with each other. Experimental results show that the PVA:Gr interface provides an improvement in the electrical parameters of MPYs. [ABSTRACT FROM AUTHOR]

This paper estimates the robustness of non-volatile device (NVM) Gadolinium (Gd) doped Hafnium oxide (HfO2)nanoparticles (NPs) based memristor which was constructed using as-formed and annealed nanoparticles in 600 °C and 800 °C temperature, based on their performance in various basic image processing applications (i.e. edge detection filter and noise-canceling filter). A catalytic free glancing angle deposition technique (GLAD) is employed to grow Gd doped HfO2 nanoparticles (NPs) of 8 nm range on the thin film of Silicon oxide SiOx in 30 nm dimension. Annealing process is performed on Gd-doped HfO2 NPs and and the changes were demonstrated in its surface morphology. The elemental composition of the device was analyzed by Energy Dispersive X-ray (EDX). Photoluminescence (PL) analysis revealed that the topography and electrical characteristics of Gd-doped HfO2 alter swiftly after annealing process. A leakage current, interface state density (Dit) factor emphasizes that the device annealed at 600 °C portrayed significant improvement in the non-volatile characteristics in comparison with other devices. Additionally, the endurance of the device annealed at 600 °C was seen to possess more than decades of memory potential. The C-V and hysteresis curve measurement demonstrated maximal charge accumulation relative to other devices. Crossbar array is designed from both as-formed and annealed memristor devices.

Abstract The interfacial and electrical properties of atomic layer deposited AlN on n-GaN with different AlN thicknesses were investigated. According to capacitance–voltage (C–V) characteristics, the sample with a 7.4-nm-thick AlN showed the highest interface and oxide trap densities. When the AlN thickness was 0.7 nm, X-ray photoelectron spectroscopy (XPS) spectra showed the dominant peak associated with Al–O bonds, along with no clear AlN peak. The amount of remained oxygen atoms near the GaN surface was found to decrease for the thicker AlN. However, many oxygen atoms were present across the AlN layer, provided the oxygen-related defects, which eventually increased the interface state density. The barrier inhomogeneity with thermionic emission (TE) model was appropriate to explain the forward bias current for the sample with a 7.4-nm-thick AlN, which was not proper for the sample with a 0.7-nm-thick AlN. The reverse leakage currents for both the samples with 0.7- and 7.4-nm-thick AlN were explained better using Fowler–Nordheim (FN) rather than Poole–Frenkel emissions.

Thermally grown SiO2 is widely used for silicon surface passivation in solar cells and other applications due to excellent interfacial properties. SiO2 films with thickness in the range of 17 nm deposited by industrially viable spray-coating technique on both n- and p-type silicon are reported. Low values of interface state density of 1.4 × 1010 cm−2 eV−1 on n-type and 2.0 × 1010 cm−2 eV−1 on p-type were achieved. Fixed oxide charges in the range of 7.1– 9.4 × 1011 cm−2 and 3.9– 6.5 × 1011 cm−2 on n- and p-type, respectively, are obtained. Excellent passivation results in the effective surface recombination velocity of 0.97 cms−1 and 8.07 cms−1 at minority carrier concentration of 1015 cm−3 on n- and p-type Czochralski silicon, respectively, without the use of capping layer. SiO2 film exhibits dielectric breakdown field strength of 4.3 MV cm−1 and 5.6 MV cm−1 and leakage current density of 2.2 × 10−8 A cm−2 and 1.1 × 10−8 A cm−2 at 1 MV cm−1 on n- and p-type silicon, respectively. These values are superior to sol-gel-based SiO2 films reported previously and are comparable to or better than those reported for other methods for the growth or deposition of SiO2 on silicon. Amorphous nature of the film is validated by high-resolution transmission electron microscopy (TEM). The X-ray photoelectron spectroscopy (XPS) analysis shows nearly stoichiometric SiOx film. [ABSTRACT FROM AUTHOR]

In the past few years, thin-film transistor (TFT) technology has experienced a rapid transition from amorphous silicon- (a-Si:H) and polysilicon-based TFTs to zinc oxide (ZnO)-based TFTs, and because of this transition, transparent TFTs have become a reality. In ZnO TFTs, which operate in accumulation mode, the threshold voltage has remained ambiguous due to the existence of grain boundary traps in the polycrystalline semiconducting channel. This paper provides an analytical relationship of threshold voltage with grain boundary trap density by assuming the grain boundary is a continuous one-dimensional line charge. A high density of grain boundary traps leads to a high threshold voltage. However, its effect can be minimized by employing a high-κ gate dielectric. In this work, we have demonstrated the reduction of threshold voltage in a ZnO TFT by using ZrO2 as a gate dielectric. A study of a ZnO/ZrO2 interface is reported by fabricating a metal–insulator–semiconductor capacitor structure. This interface is studied using capacitance–voltage (C–V) and current–voltage (I–V) characteristics. The ZnO TFT with a ZrO2 gate dielectric exhibits a low subthreshold slope (131 mV decade−1), low gate leakage current density (2.94 × 10−7 A cm−2) and low threshold voltage (1.2 V). However, it also exhibits a counterclockwise hysteresis of −1.4 V, which is attributed to the existence of oxygen vacancies. [ABSTRACT FROM AUTHOR]

This article reports that the enhanced forward gate bias time-dependent dielectric breakdown (TDDB) reliability and interface quality are achieved in 5-nm ferroelectric Hf0.5Zr0.5O2 (HZO) technologies by using the NH3 plasma interfacial layer (IL) treatment and microwave annealing (MWA). An orthorhombic crystalline phase is observed in the annealed HZO film with NH3 plasma IL treatment and MWA, and NH3 plasma IL treatment can suppress Hf/Zr interdiffusion. Metal-oxide-semiconductor capacitors (MOSCAPs) subjected to NH3 plasma IL treatment and 2100-W MWA also have a higher extrapolated operating voltage for a ten-year lifetime at 0.01% failure and lower interface state density (Dit) compared to the devices subjected to only rapid thermal annealing (RTA) at 600 °C. Therefore, NH3 plasma treatment and MWA are effective for improving the TDDB reliability and interface quality of the ultrathin ferroelectric HZO. [ABSTRACT FROM AUTHOR]

In this research, the significant role of 1,4,5,8-naphthalenetetracarboxylic-dianhydride, NTCDA, thin film on the Al/p-Si barrier under different temperatures is investigated. The structural and topographical properties of the thermally evaporated NTCDA thin film are investigated using a transmission electron microscope, TEM, and atomic force microscope, AFM, respectively, and elucidated that the fabricated films have a smooth nanocrystalline nature with an average crystallite size about 89 nm and average roughness about 3.15 nm. Furthermore, the current–voltage (I–V) characteristics of Al/NTCDA/p-Si/Al device are studied under dark conditions at different temperatures (313–383 K). The Schottky diode electronic parameters such as ideality factor, n, barrier height, ΦB, and reverse saturation current, Is, are calculated at each temperature. A clear increment of ΦB from 0.74 to 0.88 eV accompanied by a clear decrement of n values from 5.83 to 4.99 under increasing temperature (313–383) K is noticed. Due to the inhomogeneity of barrier height, the Gaussian distribution of Schottky barrier height is employed to estimate the mean value of barrier height and standard deviation and found to be 1.5 eV and 20 mV, respectively. The modified Richardson plot is used to estimate the modified Richardson constant and found to be 35.2 A cm−2 K−2 which is close to the known value of p-Si. Moreover, the conduction mechanism in forward and reverse biasing is explained in details. The modified Norde's function is employed for estimating the series resistance, Rs, and barrier height of the fabricated device at each temperature, where the values of Rs showed a decrement behavior from 3.564 to 1.165 kΩ upon increasing the temperature. The process of inserting NTCDA between electrode and p-Si influenced the distribution of interface states for MIS Schottky diode at different temperatures and is explained as a passivation process of the device's interface states. [ABSTRACT FROM AUTHOR]

The work reveals the design of Au/dysprosium oxide (Dy 2 O 3)/n-GaN metal/insulator/semiconductor (MIS)-type structures with a dysprosium oxide interlayer and investigates its microstructural and chemical states using XRD, TEM and XPS approaches. The outcomes confirm that the Dy 2 O 3 film exists on the n-GaN. The electrical properties of the MIS structure are probed by I–V and C–V procedures. A superior rectifying type with a small leakage current was acquired for the MIS structure rather than the Au/n-GaN Schottky diode (SD). Results showed that the MIS structure has a better barrier height (Φ b) (0.91 eV) than the SD (0.82 eV), representing that the Dy 2 O 3 layer modifies the Φ b. Using Cheung's, Norde and Ψ SP -V plots, the Φ b of the SD and MIS structure are derived and the values are nearly similar, representing that the approaches applied here are valid. The predicted N SS of the MIS structure is two orders smaller than the SD, implying that the Dy 2 O 3 interlayer substantially lowers the N SS. The Poole-Frenkel emission is the foremost current transport at a lower bias, though Schottky emission (SE) is ruled as the current transport at a higher bias of the SD. Nevertheless, the SE is prevailing in the current transport in the MIS structure. Consequences endorse that the Dy 2 O 3 layer can be suitable for building of MIS/MOS devices. [Display omitted] • Structural features of Dy 2 O 3 films were assessed by XRD and TEM. • Electrical properties of Au/n-GaN SD and Au/Dy 2 O 3 /n-GaN MIS structure were explored. • Higher barrier height was achieved for the MIS structure than the SD. • Density of states of the MIS structure was smaller than the SD. • Current conduction process was examined for the SD and MIS structure. [ABSTRACT FROM AUTHOR]

In this paper, the effect of atomic layer deposition-derived laminated interlayer on the interface chemistry and transport characteristics of sputtering-deposited Sm2O3/InP gate stacks have been investigated systematically. Based on X-ray photoelectron spectroscopy (XPS) measurements, it can be noted that ALD-derived Al2O3 interface passivation layer significantly prevents the appearance of substrate diffusion oxides and substantially optimizes gate dielectric performance. The leakage current experimental results confirm that the Sm2O3/Al2O3/InP stacked gate dielectric structure exhibits a lower leakage current density than the other samples, reaching a value of 2.87 × 10−6 A/cm2. In addition, conductivity analysis shows that high-quality metal oxide semiconductor capacitors based on Sm2O3/Al2O3/InP gate stacks have the lowest interfacial density of states (Dit) value of 1.05 × 1013 cm−2 eV−1. The conduction mechanisms of the InP-based MOS capacitors at low temperatures are not yet known, and to further explore the electron transport in InP-based MOS capacitors with different stacked gate dielectric structures, we placed samples for leakage current measurements at low varying temperatures (77–227 K). Based on the measurement results, Sm2O3/Al2O3/InP stacked gate dielectric is a promising candidate for InP-based metal oxide semiconductor field-effect-transistor devices (MOSFET) in the future.

An Au/Ni/β-Ga2O3 Schottky barrier diode was fabricated on an 8.6-μm-thick lightly doped drift region grown on heavily doped Ga2O3 substrate, and its electrical and low-frequency noise characteristics were investigated. The diode showed excellent rectifying behavior with the reverse current being saturated with the applied bias and a magnitude of ∼ 10−13 A. The diode exhibited a barrier height of 1.04 eV and a reasonably high reverse breakdown voltage of 540 V without employing any edge termination methods. The Schottky barrier parameters, such as barrier height, ideality factor, and series resistance, were obtained using a range of methods and found to be in close agreement with each other. The interface state density of the Au/Ni/β-Ga2O3 Schottky diode obtained from the capacitance–voltage (C–V) method was lower than that determined from the forward current–voltage (I–V) characteristics, attributed to the inhomogeneous distribution of interface states at the interface. An analysis of the forward log I–log V plot of the Au/Ni/β-Ga2O3 Schottky diode revealed ohmic-type conduction, and space-charge-limited current dominated the carrier transport mechanisms in lower and higher voltage ranges, respectively. For bias below 0.3 V, the low-frequency noise of the Au/Ni/β-Ga2O3 Schottky diode was a linear combination of two noise components associated with uniformly distributed bulk traps of β-Ga2O3 and the charge fluctuation in the generation-recombination center. On the other hand, for bias above 0.4 eV, the noise spectral density showed a 1/f2 dependence, indicating the domination of generation-recombination noise. [ABSTRACT FROM AUTHOR]