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This study investigates the response of nanowire field-effect transistors (NWFETs) to total ionizing dose (TID), single-event transient (SET), and their coupling effects in junctionless (JL), inversion (IM), and junctionless accumulation (AC) modes. The degradation of the three modes under irradiation and the effect of device bias configuration on the electrical properties of NWFETs are analyzed, and the different effects of SET on the three modes are compared. On this basis, the influence of TID on SET current generation and the charge collection mechanism are studied, and the changes in peak current, pulse width, and collected charge of transient current under different TIDs are compared. The results show that JL mode has the worst resistance to TID and SET coupling effects, followed by IM and AC modes. [ABSTRACT FROM AUTHOR]

The fabrication complexity, leakage current, low-power operation, and cost of nano-scale devices are major concerns. To address these challenges, we propose a dual oxide-based approach to enhance the performance of the dual oxide electrically doped junction-less tunnel field-effect transistor (DO-ED-JL-TFET). For this purpose, the oxide layer ( T ox ) is vertically segmented into two sections. The lower section comprises SiO 2 (low-K dielectric), while the upper section incorporates HfO 2 (high-K dielectric). This segmentation enhances the capacitive coupling between the gate and channel area, resulting in a reduced tunneling width near the source-channel region. Moreover, a polarity gate bias (electrically doped) of PG = -1.2 V is applied to create a P + source region over the thin silicon body. The proposed device addresses challenges such as random dopant fluctuation, thermal budget, and fabrication complexity issues compared to conventional TFETs. The performance of the proposed device has been assessed in terms of variations in carrier concentrations, electric field, energy band diagram, transfer (I ds - V gs ) characteristics, subthreshold swing (SS), and switching ratio (I on /I off ). Moreover, analog/RF performance parameters such as transconductance (g m ), cutoff frequency (f T ), and gain bandwidth product (GBP) are also analyzed and compared with conventional ED-JL-TFET. Furthermore, the impact of trap charges at the oxide-semiconductor interface on device performance is investigated for reliability. Simulated results demonstrate that DO-ED-JL-TFET exhibits greater immunity to various types of ITCs compared to conventional ED-JL-TFET, making it a more reliable choice for applications in radioactive environments. [ABSTRACT FROM AUTHOR]

Moore's law, along with the International Roadmap for Devices and Systems, continues to guide the scaling of devices below 10 nm. The challenges posed by such small-dimensioned devices form the basis of the present work. A junctionless MOSFET with a triple-metal gate structure is proposed as an alternative to conventional single-gate bulk MOSFETs for future CMOS technology. The present work investigated the direct current and analog/radio frequency characteristics including the drain current (I D ), transconductance (g m) , transconductance generation factor (TGF), cut-off frequency (f T) , frequency–transconductance product (FTP), transit time (τ) , and the total resistance of the source region, drain region, and channel (R SD + CH ) for triple-metal (TM) inversion-mode (IM) and junctionless (JL) cylindrical gate-all-around (CGAA) silicon nanowire (SiNW) MOSFETs with 3-nm gate length using the Silvaco ATLAS 3D TCAD tool. The non-equilibrium Green's function and the self-consistent solution of the Schrödinger and Poisson equations were considered. The channel was taken to be lightly doped in the case of the IM TM CGAA SiNW device. The effect of the TM gate work function engineering for a SiNW channel with a diameter of 3 nm and gate oxide ( Al 2 O 3) thickness of 0.8 nm was investigated with respect to I D , g m , TGF, f T , τ , FTP, and R SD + CH , and a comparative study between the IM TM and JL TM CGAA SiNW devices was carried out with respect to these parameters. For the JL device, optimization of the doping concentration was performed to obtain the same (i) ION current and (ii) threshold voltage (VTH) as the IM device. An 8.61- and 5.72-fold reduction in IOFF was seen for the same ION and VTH for the JL versus the IM device. It was found that the TM gate variation led to a reduction in drain-induced barrier lowering (DIBL) in the IM and JL devices. The JL SiNW showed much lower DIBL of ~39.49 mV/V, a near-ideal subthreshold slope (SS) of ~60 mV/dec, and higher I ON / I OFF current ratio of ~2.98 × 1012. which is much better than the values reported in the literature for CGAA devices. Also, the JL SiNW device was found to perform better than the IM SiNW device in terms of SS, DIBL, I ON / I OFF , g m , TGF, fT, τ , FTP, and R SD + CH . [ABSTRACT FROM AUTHOR]

In this paper, a new junctionless graphene nanoribbon tunnel field-effect transistor (JLGNR TFET) is proposed as a multi-gas nanosensor. The nanosensor has been computationally assessed using a quantum simulation based on the self-consistent solutions of the mode space non-equilibrium Green's function (NEGF) formalism coupled with the Poisson's equation considering ballistic transport conditions. The proposed multi-gas nanosensor is endowed with two top gates ensuring both reservoirs' doping and multi-gas sensing. The investigations have included the IDS-VGS transfer characteristics, the gas-induced electrostatic modulations, subthreshold swing, and sensitivity. The order of change in drain current has been considered as a sensitivity metric. The underlying physics of the proposed JLGNR TFET-based multi-gas nanosensor has also been studied through the analysis of the band diagrams behavior and the energy-position-resolved current spectrum. It has been found that the gas-induced work function modulation of the source (drain) gate affects the n-type (p-type) conduction branch by modulating the band-to-band tunneling (BTBT) while the p-type (n-type) conduction branch still unaffected forming a kind of high selectivity from operating regime point of view. The high sensitivity has been recorded in subthermionic subthreshold swing (SS < 60 mV/dec) regime considering small gas-induced gate work function modulation. In addition, advanced simulations have been performed for the detection of two different types of gases separately and simultaneously, where high-performance has been recorded in terms of sensitivity, selectivity, and electrical behavior. The proposed detection approach, which is viable, innovative, simple, and efficient, can be applied using other types of junctionless tunneling field-effect transistors with emerging channel nanomaterials such as the transition metal dichalcogenides materials. The proposed JLGNRTFET-based multi-gas nanosensor is not limited to two specific gases but can also detect other gases by employing appropriate gate materials in terms of selectivity. [ABSTRACT FROM AUTHOR]

In this paper, a new junctionless graphene nanoribbon tunnel field-effect transistor (JLGNR TFET) is proposed as a multi-gas nanosensor. The nanosensor has been computationally assessed using a quantum simulation based on the self-consistent solutions of the mode space non-equilibrium Green’s function (NEGF) formalism coupled with the Poisson’s equation considering ballistic transport conditions. The proposed multi-gas nanosensor is endowed with two top gates ensuring both reservoirs’ doping and multi-gas sensing. The investigations have included the IDS-VGS transfer characteristics, the gas-induced electrostatic modulations, subthreshold swing, and sensitivity. The order of change in drain current has been considered as a sensitivity metric. The underlying physics of the proposed JLGNR TFET-based multi-gas nanosensor has also been studied through the analysis of the band diagrams behavior and the energy-position-resolved current spectrum. It has been found that the gas-induced work function modulation of the source (drain) gate affects the n-type (p-type) conduction branch by modulating the band-to-band tunneling (BTBT) while the p-type (n-type) conduction branch still unaffected forming a kind of high selectivity from operating regime point of view. The high sensitivity has been recorded in subthermionic subthreshold swing (SS < 60 mV/dec) regime considering small gas-induced gate work function modulation. In addition, advanced simulations have been performed for the detection of two different types of gases separately and simultaneously, where high-performance has been recorded in terms of sensitivity, selectivity, and electrical behavior. The proposed detection approach, which is viable, innovative, simple, and efficient, can be applied using other types of junctionless tunneling field-effect transistors with emerging channel nanomaterials such as the transition metal dichalcogenides materials. The proposed JLGNRTFET-based multi-gas nanosensor is not limited to two specific gases but can also detect other gases by employing appropriate gate materials in terms of selectivity.

The increasing demand of portable gadgets for emerging VLSI applications call for the low power 6 T static random-access memory (SRAM) cell design. In this work, a 6 T SRAM cell has been designed using Negative Capacitance Junctionless FinFET (NC-JL FinFET) device. Further, the NC-JL FinFET based 6 T SRAM cell is evaluated for its power, stability and delay performance for read, write, and hold states and compared with conventional JL FinFET and published JL FinFET based SRAM. To investigate the reliability, the impact of ferroelectric thickness (T FE) and supply voltage (V DD) on the performance of NC-JL FinFET SRAM has also been investigated. It is shown that NC-JL FinFET SRAM dissipates 20% and ∼33% less static and dynamic power, with 1.2-, 1.5- and 1.18-times enhanced static noise margins in read, write, and hold state, respectively than JL FinFET SRAM. It also provides 37% and 20% faster read and write operations. • NC-JL FinFET based SRAM offers better stability, reliability with low power. • It dissipates 20% and 30% less static and dynamic power, respectively. • NC-JL FinFET SRAM is 37% and 20% faster during read and write operation. • It also offers almost 1.5 times higher static noise margin. • NC-JL FinFET SRAM with T FE of 2 nm provides lowest power dissipation. [ABSTRACT FROM AUTHOR]

The gate-induced drain leakage (GIDL) current is one of the important short channel effects. It is very significant to study the GIDL current (IGIDL) in negative capacitance-based FETs as the additional ferroelectric layer affects the electric field as well as band-to-band tunneling. This article proposed an analytical model for GIDL current in negative capacitance junctionless FinFET (NC-JL FinFET). This model is based on tunneling mechanism and the impact of the negative capacitance is taken into consideration through LK equation. Further, the influence of various physical parameters like ferroelectric thickness, fin thickness, fin height, etc. on IGIDL of NC-JL FinFET has been also examined. It is determined that the thinner ferroelectric layer as well as fin will provide better IGIDL. It has been found that this model is computationally efficient and easy to realize, and the clearly verified results emphasize its accuracy. [ABSTRACT FROM AUTHOR]

In this work, we have proposed an extraction method for equivalent oxide thickness (EOT) of a thin high-dielectric-constant ($\kappa $) gate insulator (GI) through direct capacitance–voltage (${C}$ – ${V}$) measurements in amorphous indium tungsten oxide (a-IWO) nano-sheet (NS) junctionless (JL) transistors (a-IWO NS-JLTs). Without additional metal/insulator/Si-substrate (MIS) ${C}$ – ${V}$ measurements, the proposed extraction method can directly extract EOT (or equivalent $\kappa $ values) of a thin HfO2GI at different ON-state gate voltages (${V}_{G}$) in a-IWO NS-JLTs. Results of ${C}$ – ${V}$ measurements show that the extracted EOT varies with ON-state ${V}_{G}$ owing to the gate-controllable conductance of the amorphous oxide semiconductor (AOS) NS channel. Finally, the extracted EOT can be used to estimate the field-effect mobility ($\mu _{\text{FE}}$) of a-IWO NS-JLTs at different ON-state ${V}_{G}$. [ABSTRACT FROM AUTHOR]

In this paper, dopingless nanotube MOSFET (DL-NT MOSFET) has been designed for low power circuit applications. Performance parameters of proposed device are extracted and compared with junctionless nanotube (JL-NT MOSFET). DL-NT MOSFET has low ON current and less sensitivity towards the various device design parameter variation than heavily doped JL-NT MOSFET. It has also been observed that Subthreshold slope (SS), DIBL, ION,and IOFF current of DL-NT MOSFET has shown least sensitivity on gate length variation as compared to JL-NT MOSFET. Sensitivity towards the temperature variations has also been analysed for both the devices. DL-NT MOSFET shows very less changes in SS and DIBL ION, and IOFF current on temperature variation as compared to JL-NT MOSFET. Therefore, DL-NT MOSFET with suitable design parameters and dielectric material may be used for low power digital circuits. [ABSTRACT FROM AUTHOR]

In this work, a Schottky junction on the drain side employing low workfunction (WF) metal is proposed as a method to suppress the OFF-state leakage in nanowire (NW) field-effect transistor (FET). Instead of a highly n+ doped drain, low WF metal with negative electron Schottky barrier height (SBH) as a drain minimizes the lateral band-to-band tunneling (L-BTBT) considerably. L-BTBT is the movement of carriers (holes) from the drain conduction band into the channel valence band during the OFF-state. Impact of varying WF at channel–drain junction on the device characteristics is studied. It is observed that SBH ⩽ 0 eV is required to mitigate L-BTBT compared to the conventionally doped and junctionless (JL) NW counterpart. Furthermore, unlike L-BTBT, leakage in NW Schottky drain (SD) comprises of holes tunneling through the SB from the metal drain into the channel and is termed as the lateral SB tunneling (L-SBT). In contrast with JL NW FET, the process variation immunity (varying channel doping, N Ch and NW diameter, d NW ) and the ON-state current of the proposed device are not compromised at the expense of lower OFF-state L-SBT. Instead, the device is less susceptible to process variations and retains the ON-state performance of the NW MOSFET. For a ± 20% change in N Ch , Δ I OFF / I OFF of 7% compared to 97% in NW JL FET is observed. [ABSTRACT FROM AUTHOR]

In this work, we perform the sensitivity analysis of negative-capacitance (NC) junctionless (JL) transistors considering the variation in device parameters and compared its performance with conventional JL devices. The OFF-current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) of the JL transistor degrades significantly as the film thickness (${T}_{{\text {si}}}$), channel doping (${N}_{\text {ch}}$), and oxide thickness (${T}_{\text {ox}}$) increase and the gate length (${L}_{g}$) decreases. However, compared to JL devices, ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ degradation due to increasing ${T}_{\text {si}}$ and ${N}_{\text {ch}}$ and decreasing ${L}_{g}$ can be effectively mitigated in NCJL devices. The reduced ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ and lower $I_{ \mathrm{\scriptscriptstyle OFF}}$ sensitivities in the NCJL transistor are due to the occurrence of more negative internal gate voltage at higher ${T}_{{\text {si}}}$ and ${N}_{{\text {ch}}}$ and lower ${L}_{g}$ , which enhances the channel depletion and reduces the ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ sensitivity. The impact of ${T}_{{\text {ox}}}$ and the spacer permittivity ($\varepsilon _{s}$) shows that reducing ${T}_{\text {ox}}$ and increasing $\varepsilon _{s}$ significantly improve the ON-current in NCJL devices due to better capacitance matching at the ON-state. Besides, for the first time, a design methodology is proposed to optimize the NCJL device for high-performance (HP) applications at ${L}_{g} = {15}$ nm. The results presented in this article serve as a guideline to extend the usability of NCJL devices for HP applications. [ABSTRACT FROM AUTHOR]

In this work, TCAD-based investigation of junctionLess (JL) architecture having double gate (DG) has been performed for visualizing the sensitivity of the device against light intensity. Comparison has been drawn between conventional DG MOSFET and DG-JL transistor (DG-JLT) under dark and light conditions. Effect of light intensity and wavelength has been modulated to optimize the device sensitivity. Higher shift in the drain current (in subthreshold region) has been observed at 0.35 μm of wavelength, i.e., more sensitive to ultraviolet (UV) light. The improved sensitivity of DG-JLT as compared to DG-MOSFET is due to the better subthreshold characteristics of the device (i.e., lower leakage current and subthreshold slope). From the results, it can be concluded that the DG-JLT with channel doping of 1019 cm−3, 10 nm of channel thickness, and having 1 nm of oxide thickness is the best possible choice for UV photodetector due to high sensitivity and responsivity. It has also been observed that more optimizing parameters are available with DG-JLT as the DG-MOSFET is immune toward the device parameter variation. [ABSTRACT FROM AUTHOR]

As technology develops, the stacked nanosheet (NS) structure demonstrates promise for use in future technology nodes. This study demonstrated the excellent performance of stacked-NS channels with junctionless gate-all-around thin-film transistors and compared the electrical characteristics of single-NS and stacked-NS structures. The performance of the multi-gate and gate-all-around transistors was then further analyzed. The stacked gate-all-around thin-film transistor exhibited superior performance and excellent temperature design flexibility. In brief, the stacked gate-all-around structure for thin-film transistors structure has the potential to overcome the challenges associated with downscaling.

In this paper, a triple gate (TG) cavity based, polysilicon junctionless (JL) ion-sensitive field-effect transistor (ISFET) architecture has been proposed for the first time. The performance of the proposed device has been compared with conventionally doped ISFET. The effect of pH is investigated for different adhesion layers, device layer thickness (tsi), electrolyte thickness (te) and, channel lengths (L). Threshold voltage( △ V t h △ p H ) has been used as sensing metric for analysis and comparison. Besides, ION/IOFF ratio has also been measured for different pH. The average maximum threshold voltage sensitivity of the proposed device has been measured and found to be 72.5%, 49.5%, and 53.7% better than TG-conventional ISFET for different adhesion layers, device layer thickness, and channel lengths respectively. Furthermore, the effect of channel lenghth on threshold voltage sensitivity has also been studied. It is observed that the sensitivity increases with increase in channel length. The implementation and all the simulations have been performed by using the ATLAS device simulator. [ABSTRACT FROM AUTHOR]

In this article, a novel high-performance fold I shaped junctionless FinFET (FIS JL FinFET) is proposed. Compared to conventional JL FinFETs, the proposed FIS JL FinFET can realise lower off-state leakage current, lower parasitic capacitance while ensuring no degradation of the subthreshold swing. The electrical properties of the FIS JL FinFET have been extensively investigated through comprehensive discussions of the influences resulting from gate geometry engineering. [ABSTRACT FROM AUTHOR]

The operation characteristics of polycrystalline Si (poly-Si) gate-all-around (GAA) junctionless (JL) charge-trapping (CT) flash memory devices with the Zr-based stacked trapping layer were studied in this work. Devices with the Si3N4/ZrO2 stacked trapping layer show enhanced erasing speeds and comparable retention characteristics in comparison to Si3N4/HfO2 due to many shallow energy traps and smaller valance band offset in the ZrO2 layer. By inserting Al2O3 between Si3N4 and ZrO2 trapping layer, the retention and endurance characteristics are improved. The erasing speed can be further improved by a Zr-rich oxide layer near the tunneling oxide since the energy barrier can confine more injected electrons near the tunneling oxide. The retention characteristic can be improved without sacrificing the erasing speed because some of the shallow traps can be passivated by NH3 plasma treatment on ZrO2. Hence, the ZrO-based stacked trapping layer is very promising for the poly-Si GAA JL CT flash devices for nonvolatile memory applications. [ABSTRACT FROM AUTHOR]

In this article, we present a theoretical analysis of a junctionless (JL), ion-sensitive, field-effect-transistor (ISFET), self-consistently combining the electrochemical interaction between the semiconductor–insulator interface and the surrounding electrolyte medium. Incorporating charge-based core relationships for the nanowire (NW) and planar double gate (DG) JL FETs with basic relations governing the electrolyte–insulator proton exchanges, we predict the output characteristics of the NW and DG JL ISFETs with respect to pH for all the regions of operation. This hybrid charge-based approach of JL ISFETs is fully validated by COMSOL Multiphysics simulations without the need to introduce any fitting parameters. These developments are suitable for implementation in circuit simulators as well as for fast prototyping by tuning the technological parameters and estimate their impact on the device performances, including the electrolyte medium. [ABSTRACT FROM AUTHOR]

This article showcases a junctionless (JL)/ accumulation mode (AM) transistor connected with an access JL transistor-based capacitorless dynamic random access memory (2T-DRAM) cell. The access transistor (AT) is utilized to reduce the leakage and, thus, improves the retention time (RT) and sense margin (SM) of the proposed capacitorless 2T-DRAM cell. Simulation results reveal that the 2T-DRAM cell achieved a maximum SM of ~ 4.6 μA/μm with RT of ~6.5 s for a gate length (Lg) of 100 nm, almost 100 times against the ITRS prediction for modern DRAM cells. Furthermore, 2T-DRAM shows better gate length scalability with a fixed gate length of AT and achieves RT of ~100 and ~10 ms for a scaled gate length of 10 nm at 27 °C and 85 °C, respectively. The proposed 2T-DRAM cell offers better integration density (scalability) and higher energy efficiency that makes it a potential candidate for artificial intelligence (AI)/Internet-of-Things (IoT) applications. [ABSTRACT FROM AUTHOR]

As the channel length shrinks below the 10-nm regime, emerging materials, junctionless technology, and multiple-gate geometries provide an excellent combination to continue progress towards lower-cost high-performance ultrascaled devices. In this study, the double-gate junctionless (JL) graphene nanoribbon field-effect transistor (GNRFET) and its conventional counterpart (C-GNRFET) are compared in terms of short-channel effects (SCEs) using a quantum simulation. The computational approach is based on solving the Schrödinger equation using the mode-space nonequilibrium Green's function formalism coupled self-consistently with a Poisson equation in the ballistic limit. The analysis of gate length downscaling shows that the JL GNRFET exhibits better leakage current, subthreshold swing (SS), drain-induced barrier lowering, and threshold voltage roll-off in comparison with the conventional GNRFET. In addition, we reveal that a decrease in the n-type doping concentration can enhance the above-mentioned characteristics of both devices. The results indicate that the JL GNRFET can mitigate critical issues and enhance the immunity to SCEs of the GNRFET, making it a promising candidate for high-performance ultrascaled (sub-5-nm) technology. [ABSTRACT FROM AUTHOR]

In this brief, we upgrade our initial drain current compact model for triple-gate junctionless transistors (JLTs) to a continuous model satisfying the source/drain (S/D) symmetry. This is achieved by reformulating the key equations of our original model, using Lambert-function-based terminal charges. The upgraded model is compact, bulk-referenced valid in all regions of operation and it is validated through comparison with experimental data to verify its accuracy. The symmetry condition is investigated and validated performing the dc Gummel symmetry test (GST) for all derivatives up to the fifth order. [ABSTRACT FROM AUTHOR]

This article reports on logic and memory functionality of vertically stacked bidirectional junctionless (BiJL) transistor, which can be operated as nMOS or pMOS depending on the biases applied. An inverter can be realized with a single BiJL transistor. If a complement of inputs is available, then NAND, NOR, and XOR logic can also be realized through a single BiJL transistor. The thickness of separation oxide between n-type and p-type films can be utilized to either achieve hysteresis or the absence of the same. Results provide insights into device physics, operation, and showcase new viewpoints for designing logic and memory devices with vertically stacked JL architecture, thus achieving the desired functionality with a lesser number of transistors. [ABSTRACT FROM AUTHOR]

This paper reports on the usefulness of shell-doped (SD) junctionless (JL) transistor architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD topology overcomes the problem associated with shallower potential depth in heavily doped devices, thereby enhancing the retention time (RT) along with improved scalability. The use of a thinner shell for achieving high RT is beneficial as it reduces generation and recombination of holes. The results show that an undoped core region with shell thickness (${T}_{\textsf {Shell}}$) of 2 nm yields maximum retention. An SD (${N}_{\mathrm {d}}$) of $10^{18}$ cm $^{-\textsf {3}}$ attains RT of ~5.5 s and ~630 ms at 27 °C and 85 °C, respectively, whereas higher ${N}_{\textsf {d}}$ ($10^{19}$ cm $^{-\textsf {3}}$ shows RT of ~13ms at 85 °C for ${L}_{\textsf {g}} = \textsf {200}$ nm. SD JL transistor shows less degradation in RT with temperature. A 10 nm SD JL device with RT of ~11 ms at 85 °C demonstrates applicability as 1T-DRAM at shorter gate lengths. [ABSTRACT FROM AUTHOR]

In this paper, we propose a model for estimating short-channel effects (SCEs) in the shell-doped double-gate junctionless (JL) MOSFET. The main emphasis of this paper is to estimate SCEs by effectively capturing source/drain (S/D) extensions beyond the gate edges for different values of undoped core thickness (${T}_{\textsf {core}}$), shell doping (${N}_{\textsf {d}}$), gate length (${L}_{\textsf {g}}$), and gate (${V}_{\textsf {gs}}$) and drain (${V}_{\textsf {ds}}$) biases in subthreshold regime. The threshold voltage (${V}_{\textsf {th}}$), drain-induced barrier lowering and subthreshold swing (${S}$), extracted from transfer characteristics, are in good agreement with the simulation results. Results highlight the utility of shell doping and core thickness to provide an additional degree of freedom to control SCEs. The proposed model can be useful in estimating SCEs and optimizing core–shell JL architecture for low-power applications. [ABSTRACT FROM AUTHOR]

The electron mobility in junctionless (JL) and inversion-mode (IM) Ge nanowire nFETs with [110] channel direction is studied by theoretical calculations. Channels with different widths and cross-sectional shapes are compared. The mobility calculation is based on the Kubo–Greenwood formulation for 1-D systems. Phonon scattering, Coulomb scattering (CS), and surface roughness scattering (SRS) are considered. With the equivalent oxide thickness of 1 nm, diamond and square channels have the higher mobility than circular channels at low channel carrier density, but the lower mobility at high channel carrier density for both JL and IM channels. This mobility trend is explained by the SRS on the sharp corners in diamond and square channels. The JL channels have the lower mobility than IM channels at low channel carrier density due to additional CS. At high channel carrier density, SRS dominates, and the JL channel has the slightly higher mobility than the IM channel due to its weaker SRS. The mobility difference between JL and IM is negligible for 5-nm narrow wires. [ABSTRACT FROM AUTHOR]

The low-frequency noise in triple-gate junctionless n-MOSFETs, with channel lengths varying from 95 to 25 nm and operating in the bulk and accumulation modes, is investigated by measurements in the frequency and time domains. The experimental drain current noise spectra present $1/{f}$ and Lorentzian-type behavior components. The noise spectra in the time domain reveal that the Lorentzian-type behavior components are due to the capture and emission processes of carriers at discrete gate insulator traps, resulting in random telegraph noise (RTN). The $1/{f}$ behavior can be described by the carrier number with the correlated mobility fluctuations model. In the below-threshold region, the conducting channel is isolated from the interface by depletion region. In the above-threshold region (bulk conduction mode), the histograms of the time-domain data show multilevel switching events, from which one or more individual traps can be distinguished. The extracted time constants of two-level RTN signals indicate the interaction of a single trap either with the channel or with both channel and gate. The relative RTN amplitude is described with the carrier number with the mobility correlated fluctuations physics-based model or with the “hole in the inversion layer” stochastic simulation-based model, enabling estimation of the flat-band voltage fluctuation caused by the RTN. [ABSTRACT FROM AUTHOR]

A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high Ion/Ioff current ratio of 7 × 108 (VG = 4 V and VD = 1 V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications. [ABSTRACT FROM AUTHOR]

Junctionless (JL) nanowire is a promising candidate for the future technology nodes because it obviates the need for ultrasteep junction formation. However, with high doping (e.g., $1\times 10^{20}$ cm−3) for large on-state current ($I_{ON} $) and low contact resistance, it becomes depletion mode (${V}_{\textsf {TH}} <0$ V for nMOS and ${V}_{\textsf {TH}} > 0$ V for pMOS). In order to have enhancement-mode device (${V}_{\textsf {TH}} > 0$ V for nMOS and ${V}_{\textsf {TH}} < 0$ V for pMOS), low doping (e.g., 1019 cm−3)is required, resulting in low current and high contact resistance. We propose two structures to alleviate the problem, which allow very high doping (e.g., $1.5 \times 10^{20}$ cm−3). The proposed concepts are validated by TCAD simulations using classical and quantum (nonequilibrium Green’s function) transport models. The first one is to recess the nanowire under the gate region, resulting in enhancement-mode nMOS with >100% gain in ${I}_{ \mathrm{\scriptscriptstyle ON}}$. The second one is to have a cascode-/dual-gate structure which can further enhance ${I}_{ \mathrm{\scriptscriptstyle ON}}$ , reduce ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ and increase ${V}_{\textsf {TH}}$ with equivalent on-state gate length (${L}_{G}) = 5$ nm and off-state ${L}_{G} = 10$ nm and $50\times $ increase in ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio. Such ideas are applicable to other JL devices such as FinFET, SOI, and nanosheets. [ABSTRACT FROM AUTHOR]

In this letter, tri-gate polycrystalline silicon variable-channel junctionless transistors (VC-JLTs), which consist of a counter-doped p-type body below an n+ active device layer, are successfully demonstrated to show a better performance compared with conventional tri-gate nanosheet (NS) JLTs. Because the potential barrier between the n-channel and p-body in the VC-JLT can be controlled by the gate, the effective conduction channel behaves as a “variable” channel, in which the conduction thickness is thinner or thicker than the physical n+ thickness for the OFF or ON state, respectively. Consequently, the VC-JLT can turn OFF more efficiently due to the enhanced volume depletion and turn ON with a smaller series resistance owing to the augmented conduction volume. In addition, for the first time, the impact of the body doping concentration is investigated and the performance sensitivities of VC-JLTs in terms of ${I}_{ \mathrm{ON}}$ , ${V}_{T}$ , S.S., and DIBL are discussed with respect to the dopant redistribution. Furthermore, the quality factor (${I}_{ \mathrm{ON}}$ /S.S.) of the VC-JLT is also benchmarked with recently published poly-Si JLTs, showing that the proposed VC-JLT exhibits good S.S. and a record ${I}_{ \mathrm{ON}}$ , which makes it as a promising device for 3-D integrated nanoelectronics. [ABSTRACT FROM AUTHOR]

The device transport parameters (subthreshold slope, low-field mobility, series resistance, and threshold voltage) of n-channel triple-gate junctionless transistors are investigated in the temperature range 298–398 K. The temperature dependence of these parameters is analyzed to clarify the mechanisms responsible for the impact of temperature on the device performance. Based on analytical empirical expressions capturing their temperature dependence, our analytical compact model can predict the transfer and output characteristics at elevated temperatures with good accuracy. [ABSTRACT FROM AUTHOR]

This paper reports on the potential benefits of a vertically stacked ${n}$ - and ${p}$ -type junctionless (JL) transistor physically decoupled through an intermediate oxide layer for dynamic memory application. The proposed topology enhances the retention time (RT) of capacitorless dynamic random access memory (1T-DRAM), with a significant improvement $(\sim \!\!\times 10^{3})$ compared with a conventional JL transistor with a doping (${N}_{\text{d}}$) of 1019 cm−3. The functionality of architecture as DRAM is based on physically decoupling the conduction region (top ${n}$ -type JL transistor) and storage region (bottom ${p}$ -type JL), while maintaining an electrostatic coupling between them. The charge stored in the ${p}$ -type JL determines RT, and also impacts the read currents, and thus, influences the sense margin of DRAM. Stacked JL (SJL) 1T-DRAM achieves a maximum RT of ~2.5 s for ${N}_{\text{d}} = 5 \times 10^{18}$ cm−3 and ~1 s for 1019 cm−3 with a gate length (${L}_{\text{g}}$) of 200 nm at 85 °C. Results demonstrate its functionality down to 20 nm. The enhanced DRAM metrics (better scalability and high RT) are attributed to optimal architecture due to the vertical stacking of ${n}$ - and ${p}$ -type regions. [ABSTRACT FROM AUTHOR]

In this paper, we study the impact of vertical Gaussian doping (GD) profile and ferroelectric (FE) negative capacitance phenomenon on the performance of nanoscale double-gate junctionless (JL) transistor. The device characteristics have been obtained by using the baseline approach of combining Landau–Khalatnikov equation with TCAD simulations. Doped HfO2 has been incorporated as FE gate insulator and parameters such as coercive field (${E}_{c}$) and remanent polarization (${P}_{r}$) have been optimized to achieve nonhysteretic voltage amplification along with substantial gain. The impact of GD profile in the channel and FE gate insulator is examined by studying device characteristics for a wide range of projected range (${R}_{p}$), straggle ($\sigma$), and peak doping (${N}_{\mathbf {pk}}$) values for optimized ${E}_{c}$ and ${P}_{r}$. It has been demonstrated that the proposed device exhibits reduced leakage current, increase in ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio by 4 orders, and approximately 2 times improvement in ${g}_{m}/{I}_{d}$ values compared to the conventional double-gate GD JL transistor. Furthermore, the proposed device exhibits reverse drain induced barrier lowering effect which leads to increase in barrier even in nanoscale regime. [ABSTRACT FROM AUTHOR]

This paper reports the significance of device architecture to enhance impact ionization (I.I.) resulting in steep increase in the current from OFF- to ON-state. Recognizing that the area over which I.I. occurs is a key factor governing impact generated power per unit volume in the semiconductor film, we use raised source/drain (RSD) architecture to achieve sub-60-mV/decade subthreshold swing (S-swing) in germanium (Ge) junctionless (JL) devices at drain bias ( ${V}_{\text {ds}}$ ) of 0.9 V. The performance of RSD Ge JL device is compared with double-gate Ge JL transistor to highlight the occurrence of subthermal S-swing <5 mV/decade in RSD topology. The impact of band-to-band tunneling (BTBT) on the switching characteristics shows that RSD JL device with relatively thicker side oxide can effectively suppress BTBT while enhancing I.I. The influence of parasitic capacitance due to RSD regions and vertical doping gradient is also analyzed. Results highlight new viewpoints for the design of RSD Ge JL MOSFETs with channel doping $({N}_{\text {ch}}) \ge {5}\times {10}^{18}$ cm−3 to facilitate sharp current transition. [ABSTRACT FROM AUTHOR]

Nanowire field-effect transistors (NWFETs) have emerged as promising candidates for realization of advanced CMOS technology nodes. Due to small nanowire dimensions, NWFETs are vulnerable to the impact of process-induced random local variations, such as the line edge roughness (LER) and random dopant fluctuation (RDF). NWFETs have three different device modes, namely, the inversion mode (IM), the accumulation mode (AM), and the junctionless (JL) mode. In this paper, a 3-D quasiatomistic LER model is used for the analysis of LER-induced mismatch in JL, IM, and AM NWFETs. We have also compared the impact of 3-D LER with that of 2-D LER. In addition, another emerging simulation methodology known as statistical impedance field method is utilized to analyze the impact of RDF on the three flavors of NWFETs. We show that JL NWFETs have much higher mismatch due to both LER and RDF than their IM and AM NWFET counterparts with otherwise identical device structure. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the impact of gate-source/drain underlap on short-channel behavior of junctionless (JL) transistor through a quasi-analytical model and 2-D numerical simulations. The proposed five-region model for potential is developed for the symmetric mode operation of double-gate (DG) JL MOSFET in the subthreshold regime, to predict and minimize short-channel effects (SCEs) using the optimum design of underlap regions. The five-region model can be transformed into four or three regions to incorporate the possible dependence of biases, doping, and gate workfunction with the underlap length. The parameters indicating SCEs can also be extracted using an analytical approximation for sub-threshold drain current. The results from the proposed model are in reasonable agreement with simulation data. Analyses show that underlap length is a critical parameter to restrict the lateral extension of depletion region into the ungated portion. With increasing the underlap length, SCEs improve prominently for moderate doping concentration (1018 cm-3). The improvement in SCEs ceases once the device achieves the maximum lateral extension of the depletion region. This paper provides the physical insights into the optimal use of underlap region in nanoscale JL devices for suppressing SCEs. [ABSTRACT FROM AUTHOR]

This paper demonstrates the influence of nonuniform doping on the electrostatics of symmetric double-gate junctionless transistor using empirical modeling scheme. To present the clear insight into the device electrostatics of nonuniform doped channel, the peak of the doping concentration has been varied from Si/SiO2 interface of front gate to the back gate. The parameters explored in this paper are surface potential, electric field, drain current, threshold voltage, subthreshold slope, and drain-induced barrier lowering for different straggle factors and channel lengths. By properly optimizing the straggle value and peak of the doping concentration, device performance can be tuned accordingly. [ABSTRACT FROM AUTHOR]

In this letter, a junctionless (JL) poly-Si thin-film transistor (TFT) with a 3-nm-thick nanosheet channel is successfully fabricated using the low-temperature atomic level etching process. An inversion-mode (IM) TFT is also prepared for performance comparison and reliability investigation of positive gate bias stress (PGBS). In comparison with the IM-TFT, the JL-TFT exhibits superior PGBS reliability. The origin of the difference in degradation rates between the JL and IM-TFTs is ascribed to the different transport mechanisms and different gate dielectric fields under the same gate over-drive stress. Nanosheet JL-TFTs with a 3-nm channel thickness show excellent S.S (69 mV/decade) and extremely low off-current (1.93 fA). Results indicate that it is a promising candidate for low-power 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

In this work, the negative capacitance phenomenon exhibited by ferroelectric materials has been incorporated in Junctionless Cylindrical Surrounding Gate (JLCSG) transistor and an analytical model has been developed to study the electrical characteristics of the device by taking into account Landau Khalatnikov equation along with parabolic potential approximation. Using the derived model various electrical parameters such as potential, gain, drain current, gate capacitance etc have been obtained. Silicon doped hafnium oxide has been incorporated as the ferroelectric material and exhaustive study has been done to study the impact of interfacial layer and metal workfunction on device characteristics as these have significant impact on the performance of Junctionless devices. It has been demonstrated by analytical model and TCAD simulations that by incorporating ferroelectric layer and optimizing metal work function and interfacial layer thickness, the device performance of JLCSG can be substantially improved. [ABSTRACT FROM AUTHOR]

In this paper, we report on the reduction of the off-state band-to-band tunneling (BTBT) while maintaining sub-60 mV/decade switching in Germanium (Ge) Junctionless (JL) transistor through well-calibrated simulations. Recognizing the product of current density ( J ) and electric field ( E ) to be the key generic parameter governing device optimization, it is shown that a device with thicker film operated at lower drain bias ( V\text {ds} ) can sustain impact ionization and limit BTBT, thereby balancing the conflicting requirements of J\cdot E for tunneling and impact ionization. An optimal workfunction and gate-to-drain underlap of 5 nm in Ge JL MOSFET can further suppress BTBT while achieving a subthreshold swing of ~5 mV/decade with nearly four decades of steep current transition at the threshold voltage along with a low off-current ( \text 10^\text -10$}}\text{A}$ ) at {V}_{\text {ds}} = \text {0.9} V. Results highlight new viewpoints for the design optimization of steep-switching Ge JL MOSFETs. [ABSTRACT FROM PUBLISHER]

This brief investigates short-channel effects (SCEs) in junctionless (JL) double-gate (DG) MOSFETs analytically by solving the 2-D potential in subthreshold. \mathrm I\mathsf {ds}-{\mathrm {V}}\mathrm {{g}} curves and \mathrm V\mathrm {{t}} rolloff generated from the model are validated by 2-D numerical simulations (Technology Computer Aided Design). It is shown that the SCE of JL MOSFETs is inherently worse than that of undoped DG MOSFETs. The SCE worsens with increasing doping concentration in the channel. [ABSTRACT FROM PUBLISHER]

In this paper, the electrical characteristics of the Pi-gate junctionless FETs (PG JL FETs) with the in situ n+ doped poly-Si (DP-Si) fin-channels have been experimentally investigated and comprehensively discussed. The subthreshold behavior and threshold voltage of the PG JL FETs are sensitive to the channel dimensions, especially the channel width. The crystallinity, carrier mobility, and effective carrier concentration in the DP-Si films are dependent on the initial DP-Si film thicknesses, which directly influence the on current and threshold voltage of the PG JL FETs. Based on an evaluation on the subthreshold behavior and the driving current, we found that the PG JL FETs with the low/high aspect ratio (A.R. = channel thickness/channel width) are separately suitable for the low-power/high-performance applications. Among these PG JL FETs, the device with a proper A.R. (3.35) exhibits a relatively steep subthreshold swing (S.S.) of 66 mV/decade and the highest ON/OFF currents ratio ( I \mathrm{\scriptscriptstyle ON}/I \mathrm{\scriptscriptstyle OFF}) of $1.2\times 10^{{8}}$ ( {V}_{D} = {1} V). These devices are very promising candidates for future multifunctional 3-D integrated circuit applications. [ABSTRACT FROM AUTHOR]

In this paper, we report on the anomalous behavior of threshold voltage ( V \sf th) with temperature in junctionless (JL) transistors. It is shown that both positive and negative values of temperature coefficient of threshold voltage (dV \sf th /dT) in nMOS Si and Ge JL devices can occur at higher drain biases. At lower temperatures, V \sf th reduces with a decrease in temperature due to the dominance of bipolar effects over thermal generation of carriers, whereas at higher temperatures, thermal generation results in essentially unipolar characteristics, and V \sf th reduces with increase in temperature. It is also shown that zero temperature coefficient condition shall be nonexistent under dominant bipolar conduction over unipolar operation. Results show new viewpoints to understand the two contrasting physical mechanisms leading to positive and negative dV \sf th /dT values in JL devices. [ABSTRACT FROM AUTHOR]

A new charge-based analytical compact model for the drain current of junctionless (JL) triple-gate MOSFETs is presented, which includes the short-channel effects, the saturation velocity overshoot, the series resistance, and the mobility degradation effects. The proposed model consists of a single analytical equation that covers the depletion operation region in which the bulk conduction determines the drain current. The model is supported by experimental measurements in JL nanowire transistors with channel length varying from 95 to 25 nm and doping concentration 2 \times 10^19 cm ^\mathrm -3 . The overall results reveal the very good accuracy of the proposed analytical compact model, making it suitable for circuit simulation tools. [ABSTRACT FROM PUBLISHER]

In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 °C-heated phosphoric acid (HPA) was adopted for trimming the channel dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the channel dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing ~75 mV/decade, low drain-induced barrier lowering ~33 mV/V, and high on/off currents ratio ( I\mathrm{\scriptscriptstyle ON}/I\mathrm{\scriptscriptstyle OFF}) \sim 7 \times 10^{6} can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future. [ABSTRACT FROM PUBLISHER]

The electron mobility in junctionless (JL) Ge nanowire nFETs with the $\langle 110\rangle $ channel direction is calculated and compared with experimental data. The calculation of the electron mobility is based on the Kubo–Greenwood formula. The wave functions are obtained by solving the self-consistent Poisson–Schrödinger equation. Phonon scattering, surface roughness scattering, and Coulomb scattering (CS) by interface charges and channel charges are considered. Carrier screening on Coulomb charges is calculated using Lindhard’s screening theory. At low electron densities, the JL channels have lower electron mobility than inversion-mode (IM) channels due to CS from channel charges. At high electron densities, CS in JL channels is effectively reduced by screening, resulting in mobility comparable with the IM channels. The L4 electrons have higher mobility than \text{L}4^\prime electrons. Applying uniaxial tensile strain along the channel can lower the energy of L4 valleys to enhance the channel mobility. [ABSTRACT FROM AUTHOR]

In this paper, the Pi-gate (PG) poly-Si junctionless (JL) and inversion mode (IM) FETs with a high aspect ratio (A.R. = channel thickness/channel width ~ 3.4) have been successfully fabricated and demonstrated by a method without using the costly lithography technique. This method has some advantages: 1) the thickness of channels can be controlled simply by thickness of poly-Si layer; 2) the shape of channels can be controlled effectively by rectangular silicon nitride (Si3N4) as hard masks; 3) the series resistance can be reduced by raised source/drain configurations; and 4) Si-compatible low thermal budget process. The PG poly-Si JL FETs show excellent electrical performance in terms of low gate overdrive voltage ( VG – V\mathrm{ TH} = 2 V), extremely near-ideal subthreshold swing (S.S.) ~68 mV/decade, steep average subthreshold swing (A.S.S.) ~ 73 mV/decade, smaller drain-induced barrier lowering ~9 mV/V, a higher ON/OFF current ratio \sim 1.1 \times 10^8 ( \textV\mathbf {D} = 1 V), and a better field-effect mobility ( \mu \mathrm{ FE}) \sim 35 (cm2/Vs) as compared with PG poly-Si IM FETs. Thus, these devices are very promising for future 3-D integrated circuits applications. [ABSTRACT FROM AUTHOR]