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ABSTRACT In this paper, a robust low‐power power‐on‐reset (POR) circuit with dual threshold method is proposed. The current‐based circuit exhibits good robustness with respect to process, voltage, temperature, and supply ramp variations. In contrast to conventional delay‐based pulse generation approaches, a dual threshold method is introduced to generate POR and brown‐out‐reset (BOR) pulse signals, resulting in ultralow quiescent current and a compact area. Implemented in the 55‐nm CMOS process, the proposed circuit achieves an accurate trigger‐point voltage with a temperature coefficient of 90.4 ppm/°C and a deviation to the ramp time of 2.9% for a range from 100 μs to 1 s. Furthermore, the quiescent current and active area are 0.3 nA and 4834 μm2, respectively, making it particularly suitable for energy harvesting systems. [ABSTRACT FROM AUTHOR]

Neural networks (NNs) have proven their ability to deal with many computer vision tasks, including image-based remote sensing such as the identification and segmentation of hyperspectral images captured by satellites. Often, NNs run on a ground system upon receiving the data from the satellite. On the one hand, this approach introduces a considerable latency due to the time needed to transmit the satellite-borne images to the ground station. On the other hand, it allows the employment of computationally intensive NNs to analyze the received data. Low-budget missions, e.g., CubeSat missions, have computation capability and power consumption requirements that may prevent the deployment of complex NNs onboard satellites. These factors represent a limitation for applications that may benefit from a low-latency response, e.g., wildfire detection, oil spill identification, etc. To address this problem, in the last few years, some missions have started adopting NN accelerators to reduce the power consumption and the inference time of NNs deployed onboard satellites. Additionally, the harsh space environment, including radiation, poses significant challenges to the reliability and longevity of onboard hardware. In this review, we will show which hardware accelerators, both from industry and academia, have been found suitable for onboard NN acceleration and the main software techniques aimed at reducing the computational requirements of NNs when addressing low-power scenarios. [ABSTRACT FROM AUTHOR]

Many low‐power technologies have been developed for high‐performance displays. One method is to vary the refresh rate according to the input image, where frequencies are reduced over still images and slow‐moving videos. To support the variable refresh rate scheme, the programmable gate driver circuit should be integrated. This paper proposes a thin‐film transistor (TFT) shift register of which output pulse is simply controlled by an enable signal. Because the output pulse generation is directly adjusted without the previous programming period, various output pulse sequences are possible with the high flexibility. The shift register is composed by adding six TFTs and one capacitor to a conventional circuit that provides a carry pulse to a next stage. The simulation program with integrated circuit emphasis (SPICE) simulation ensures that gate pulses for any numbers of lines in any regions can be generated within one frame only by applying the enable signal at the corresponding timing, resulting in multiple refresh frequencies in a screen. In addition, it is verified that additional TFTs and capacitor contribute to only the negligible increase in power consumption by 2.1%, compared to a conventional shift register. [ABSTRACT FROM AUTHOR]

Active mobility and light vehicles, such as e-bikes, are gaining increasing attention as sustainable transportation alternatives to internal combustion solutions. In this context, collecting comprehensive data on environmental conditions, vehicle performance, and user interaction is crucial for improving system efficiency and user experience. This paper presents a data acquisition system designed to collect data from multiple sensor platforms. The architecture is optimized to maintain low power consumption and operate within limited computational resources, making it suitable for real-time data acquisition on light vehicles. To achieve this, a data acquisition module was developed using a single-board computer integrated with a custom shield, which also captures data related to the assistance of an e-bike motor through a wireless interface. The paper provides an in-depth discussion of the architecture and software development, along with a detailed overview of the sensors used. A demonstrator was created to verify the system architecture idea and prove the potentialities of the system overall. The demonstrator has been qualified by professional and semi-professional riders in the framework of the Giro-E, a cyclist event which took place in May 2024, on the same roads of the Giro d'Italia. Finally, some preliminary analyses on the data acquired are provided to show the performance of the system, particularly in reconstructing the user behavior, the environmental parameters, and the type of road. [ABSTRACT FROM AUTHOR]

In this paper, we propose an ultrascaled WS2 field-effect transistor equipped with a Pd/Pt sensitive gate for high-performance and low-power hydrogen gas sensing applications. The proposed nanosensor is simulated by self-consistently solving a quantum transport equation with electrostatics at the ballistic limit. The gas sensing principle is based on the gas-induced change in the metal gate work function. The hydrogen gas nanosensor leverages the high sensitivity of two-dimensional WS2 to its sur-rounding electrostatic environment. The computational investigation encompasses the nanosensor's behavior in terms of potential profile, charge density, current spectrum, local density of states (LDOS), transfer characteristics, and sensitivity. Additionally, the downscaling-sensitivity trade-off is analyzed by considering the impact of drain-to-source voltage and the electrostatics parameters on subthreshold performance. The simulation results indicate that the downscaling-sensitivity trade-off can be optimized through enhancements in electrostatics, such as utilizing high-k dielectrics and reducing oxide thickness, as well as applying a low drain-to-source voltage, which also contributes to improved energy efficiency. The proposed nanodevice meets the prerequisites for cutting-edge gas nanosensors, offering high sensing performance, improved scaling capability, low power consumption, and complementary metal–oxide–semiconductor compatibility, making it a compelling candidate for the next generation of ultrascaled FET-based gas nanosensors. [ABSTRACT FROM AUTHOR]

In this paper, a novel master-slave flip-flop is designed that incorporates 15 transistors and a single-phase clock, employing topological and adaptive coupling methods. The proposed flip-flop circuit (PFC) is more efficient than other logic-structured flip-flops. PFC is designed using a 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology node. Notably, the PFC exhibits an impressive 34.18%, 42.92%, 39.71%, 44.39%, and 46.91% improvement in average power consumption compared to the adaptive data track flip-flop (ADTFF), Hybrid Flip-Flop (HFF),18-transistor single-phase clocked (18TSPC), Logic Structured Reduction Flip-Flop (LSRFF), and Topologically compressed flip-flop (TCFF). It also improved the C to Q delay, power delay product (PDP). Monte Carlo simulations of average power and C to Q delay have been performed for 1000 samples. By reducing the number of PMOS transistors, the total area of the PFC is minimized. PFC operates effectively within a clock frequency range of up to 1 GHz. [ABSTRACT FROM AUTHOR]

Dissolved gas analysis (DGA) is considered to be the most convenient and effective approach for transformer fault diagnosis. Due to their excellent performance and development potential, chemiresistive gas sensors are anticipated to supersede the traditional gas chromatography analysis in the dissolved gas analysis of transformers. However, their high operating temperature and high power consumption restrict their deployment in battery-powered devices. This review examines the underlying principles of chemiresistive gas sensors. It comprehensively summarizes recent advances in low-power gas sensors for the detection of dissolved fault characteristic gases (H2, C2H2, CH4, C2H6, C2H4, CO, and CO2). Emphasis is placed on the synthesis methods of sensitive materials and their properties. The investigations have yielded substantial experimental data, indicating that adjusting the particle size and morphology structure of the sensitive materials and combining them with noble metal doping are the principal methods for enhancing the sensitivity performance and reducing the power consumption of chemiresistive gas sensors. Additionally, strategies to overcome the significant challenge of cross-sensitivity encountered in applications are provided. Finally, the future development direction of chemiresistive gas sensors for DGA is envisioned, offering guidance for developing and applying novel gas-sensitive sensors in transformer fault diagnosis. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive review of the state-of-art high-speed dynamic comparators. The comparator is a critical block of high-speed, low-power analog-to-digital converters, determining the speed and overall power consumption. Therefore, the design of a high-speed comparator with tolerable offset, noise and power consumption is of utmost importance. Recent work reported on high-speed comparator topologies is investigated in detail with the help of simulations in 65 nm CMOS technology. Various parameters, such as delay, energy consumption, speed, offset, kickback noise, power delay product, etc., are compared. A detailed comparative study is also presented on several design methodologies. [ABSTRACT FROM AUTHOR]

To compare low- vs high-power HoLEP effects on coagulation in patients on antiplatelet (AP) therapy via thromboelastography (TEG). Methods: 210 patients was retrospectively analyzed and stratificated into three discrete groups, specifically: Group A (AP therapy, high-power HoLEP, n = 72); Group B (AP therapy, low-power HoLEP, n=73); Group C (no AP therapy, low-power HoLEP, n = 65). Baseline characteristics and coagulation profiles via TEG were compared. Univariate and multivariate analyses were conducted to identify independent risk factors associated with hematuria. Furthermore, parameters such as IPSS, Qmax, post-void residual volume V2 and PSA levels were recorded during 1year follow-up. Results: No differences in terms of baseline characteristics across all groups. Significant differences were observed in the duration of enucleation, morcellation, bladder irrigation, post-operative catheterization, length of hospital stay and the extent of hemoglobin reduction (F = 54.06, 8.54, 6.68, 9.24, 17.06, 5.97, p <  0.05). No differences were noted in postoperative hematuria, urine retention, transfusion rates, and SUI (x12 = 1.082 ; x22 =  0.197,; x32 =  3.981;x42 =  0.816, p >  0.05). Univariate and multivariate analyses revealed that prostate volume emerged as an independent risk factor for hematuria (OR 1.080, 95% CI: 1.007– 1.158, p =  0.031). Clinical outcomes including Qmax, IPSS, V2, and PSA demonstrated significant enhancement during 1 year follow-up. Conclusion: Compared to HP-HoLEP, LP-HoLEP effectively reduces surgical and subsequent processing times, decreases hospital stay duration, and diminishes hemoglobin decline, offering a viable option without discontinuing AP therapy. [ABSTRACT FROM AUTHOR]

In this paper, we present a CMOS rail-to-rail second-generation voltage conveyor (VCII) suitable for low power applications, implemented in 180 nm CMOS technology with a supply voltage of ± 0.9 V. The proposed VCII consists of a current and voltage buffer operating in class AB. At the input of the voltage buffer, there is a bulk-driven differential amplifier, which provides a rail-to-rail input common-mode voltage. A common source output stage in class AB provides rail-to-rail at the output of the voltage buffer. The transistors are designed to operate in moderate inversion, achieving a relatively large current and voltage buffer bandwidth of 298.3 MHz and 173.2 MHz, respectively, with a power consumption of 157 μW. A sine wave with an amplitude of 1.5 Vpp and a frequency of 1 MHz on the output buffer has a total harmonic distortion of only 0.29%. The application of VCII in a relaxation oscillator with a frequency of up to 10 MHz is demonstrated, as well as its comparative characteristics with reference to other relevant square-wave generators published in the literature. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Zhejiang University (Science Edition) is the property of Journal of Zhejiang University (Science Edition) Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In this paper, a comprehensive exploration is undertaken to elucidate the utilization of Spiking Neural Networks (SNNs) within the biomedical domain. The investigation delves into the experimentally validated advantages of SNNs in comparison to alternative models like LSTM, while also critically examining the inherent limitations of SNN classifiers or algorithms. SNNs exhibit distinctive advantages that render them particularly apt for targeted applications within the biomedical field. Over time, SNNs have undergone extensive scrutiny in realms such as neuromorphic processing, Brain-Computer Interfaces (BCIs), and Disease Diagnosis. Notably, SNNs demonstrate a remarkable affinity for the processing and analysis of biomedical signals, including but not limited to electroencephalogram (EEG), electromyography (EMG), and electrocardiogram (ECG) data. This paper initiates its exploration by introducing some of the biomedical applications of EMG, such as the classification of hand gestures and motion decoding. Subsequently, the focus extends to the applications of SNNs in the analysis of EEG and ECG signals. Moreover, the paper delves into the diverse applications of SNNs in specific anatomical regions, such as the eyes and noses. In the final sections, the paper culminates with a comprehensive analysis of the field, offering insights into the advantages, disadvantages, challenges, and opportunities introduced by various SNN models in the realm of healthcare and biomedical domains. This holistic examination provides a nuanced perspective on the potential transformative impact of SNN across a spectrum of applications within the biomedical landscape. [ABSTRACT FROM AUTHOR]

Chopper and capacitively coupled techniques are employed in instrumentation amplifiers to create capacitively coupled chopper instrumentation amplifiers (CCIAs) that obtain a high noise power efficiency. However, the CCIA has some disadvantages due to the chopper technique, namely chopper ripple and a low input impedance. The amplifier can easily saturate due to the chopper ripple of the CCIA, especially in extremely low noise problems. Therefore, ripple attenuation is required when designing CCIAs. To record biomedical information, a CCIA with a low power consumption and a low noise, low output ripple, and high input impedance (Zin) is presented in this paper. By introducing a ripple attenuation loop (RAL) including the chopping offset amplifier and a low pass filter, the chopping ripple can be reduced to 0.36 mV. To increase the Zin of the CCIA up to 1.8 GΩ, an impedance boost loop (IBL) is added. By using 180 nm CMOS technology, the 0.123 mm2 CCIA consumes 1.87 µW at a supply voltage of 1 V. According to the simulation results using Cadance, the proposed CCIA architecture achieves a noise floor of 136 nV/√Hz, an input-referred noise (IRN) of 2.16 µVrms, a closed-loop gain of 40 dB, a power supply rejection ratio (PSRR) of 108.6 dB, and a common-mode rejection ratio (CMRR) of 118.7 dB. The proposed CCIA is a helpful method for monitoring neural potentials. [ABSTRACT FROM AUTHOR]

A split-voltage amplifier architecture is proposed which improves the power efficiency compared to a conventional implementation. The approach is verified with a prototype fabricated in 0.35 µm CMOS technology using lateral bipolar input transistors. It achieves a measured DC gain of 105 V/V, a differential AC gain of 40.3 dB with a bandwidth of 55 kHz, a CMRR of approximately 75 dB, and a PSRR of 55 dB. The input-referred noise is 7 nV/√Hz and 923 nVrms integrated from 100 Hz to 10 kHz, resulting in a Noise Efficiency Factor (NEF) of 2.84 and a Power Efficiency Factor (PEF) of 18.3. The split-voltage configuration improves power efficiency by nearly 25% compared to a full voltage supply and maintains a small area design. Action potentials of the medial and lateral giant fiber of an earthworm are recorded as an example application. [ABSTRACT FROM AUTHOR]

Halide perovskites with naturally coupled electron‐ion dynamics hold great potential for nonvolatile memory applications. Self‐rectifying memristors are promising as they can avoid sneak currents and simplify device configuration. Here we report a self‐rectifying memristor firstly achieved in a single perovskite (NHCINH3)3PbI5 (abbreviated as (IFA)3PbI5), which is sandwiched by Ag and ITO electrodes as the simplest cell in a crossbar array device configuration. The iodide ions of (IFA)3PbI5 can be easily activated, of which the migration in the bulk contributes to the resistance hysteresis and the reaction with Ag at the interface contributes to the spontaneous formation of AgI. The perfect combination of n‐type AgI and p‐type (IFA)3PbI5 gives rise to the rectification function like a p–n diode. Such a self‐rectifying memristor exhibits the record‐low set power consumption and voltage. This work emphasizes that the multifunction of ions in perovskites can simplify the fabrication procedure, decrease the programming power, and increase the integration density of future memory devices. [ABSTRACT FROM AUTHOR]

Copyright of Informacije MIDEM: Journal of Microelectronics, Electronic Components & Materials is the property of MIDEM Society and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper proposes a power‐optimized column‐parallel cyclic analog to digital converter (ADC) for complementary metal oxide semiconductors (CMOS) image sensor readout circuits. The design combines a 2.5‐bit/cycle architecture with a comparator shutdown technique based on the comparator‐based switched‐capacitor (CBSC) circuits, which results in a significant reduction in the operating time of the threshold detection comparator compared with conventional CBSC circuits. This reduction in operating time leads to power savings as the threshold detection comparator can be shut down quickly. The paper also presents a comprehensive analysis of the nonideal factors of CBSC circuits and the coarse and fine conversion allocation scheme. The 10‐bit two‐stage comparator‐based cyclic ADC is designed in a 110 nm 1P4 M CMOS technology. Simulation results show that the effective number of bit (ENOB) is 9.7 bits, with each column consuming 103 μW of power. The proposed cyclic ADC has a figure of merit (FOM) of 123 fJ/conv‐step. Compared with conventional structures, the proposed design reduces the power consumption of the ADC by 34.3% while maintaining the same level of performance. [ABSTRACT FROM AUTHOR]

Smart door locks pose a large number of threats such as network attacks. Its storage area and power of cipher are severely limited because the wireless nodes of smart door locks are mostly battery‐powered. Therefore, effective security solutions are urgently needed. In this paper, a new lightweight block cipher with low power named LPHD is proposed to ensure the security of the master control chip of the smart door lock terminal. We design a scheme of low power S‐box and construct the two‐stage permutation layer (TP structure) suitable for LPHD by filtering the sets of 8‐bit permutations. LPHD proposes a variant of the 8‐branch generalized Feistel structure (GFS) to realize that the bits of all branches are affected in one encryption round. The problem of slow diffusion in the standard Feistel structure is solved. The key schedule adopts the nonlinear design and reuses the encryption process of LPHD. It improves the security of the cipher and reduces hardware overhead. Moreover, we evaluate the hardware implementation and security of LPHD. The results show that LPHD for the unified encryption and decryption circuits requires only 1276 Gate Equivalents (GEs) and 1.914 μW on UMC 0.18 μm, which is better than other lightweight block ciphers such as SKINNY, PRESENT, and IVLBC. In summary, LPHD provides sufficient security for the master control chip of the smart door lock terminal. [ABSTRACT FROM AUTHOR]

Summary: This paper presents a subthreshold CMOS voltage reference (VR) that utilizes self‐biased circuits. This voltage reference includes temperature compensation circuits to expand its operating temperature range and reduce its temperature coefficient. The proposed CMOS voltage reference is designed using a standard 0.18‐μm CMOS process and has a small area of only 0.005 mm2. Post‐layout simulation results demonstrate that the power consumption of the circuit at room temperature (25°C) is only 1.65 nW at a power supply voltage of 1 V. In this case, the voltage reference output is 316.56 mV, with an average temperature coefficient (TC) of 11.14 ppm/°C in a wide temperature range from −40°C to 140°C. Furthermore, the line sensitivity (LS) of the circuit is 0.024%/V, and the power supply rejection ratio (PSRR) of the circuit is −86.5 dB at 10 Hz. In summary, the subthreshold CMOS voltage reference structure proposed in this paper demonstrates excellent performance characteristics, such as low power consumption, a small area, and high‐temperature stability. These features make it a promising candidate for voltage reference for low‐power applications with significant changes in environmental temperature. [ABSTRACT FROM AUTHOR]

This study introduces an artificial intelligence system implemented on the ESP32-CAM platform, aimed at conducting optical character recognition (OCR) on water meters. Leveraging LoRa technology for data transmission ensures efficient energy utilization and convenient long-range communication capabilities. The system achieves an impressive accuracy rate of 98.2% in identifying water meter readings, showcasing its reliability. Proposed as a feasible solution, it offers the advantages of low energy consumption, cost-effectiveness, and flexibility in widespread deployment, particularly leveraging existing water meter infrastructure. Thus, this research presents a promising choice for various applications beyond merely reading water meter readings. Its efficient and accurate OCR functionality makes it suitable for diverse scenarios, ranging from smart city initiatives to industrial automation processes. With its ability to integrate seamlessly into existing infrastructure and deliver reliable results, this system stands poised to revolutionize OCR applications in various domains, contributing to enhanced efficiency and productivity.

The overall performance of any integrated circuit is defined by its proper memory design, as it is a mandatory and major block which requires more area and power. The prime interest of this article is to design a memory structure which is tolerant to variations in CNFET (Carbon nanotube field effect transistor) parameters like pitch, diameter and number of CNT tubes, and also offer low power and high speed of operation. In this context, CNFET based stacked SRAM (Static random access memory) design is proposed to attain the above mentioned criteria. Concept of stack effect is utilized in the cross coupled inverter section of the memory structure to attain low power. The power, speed and energy analysis for the proposed structure is done, and compared with the conventional structures to justify the proposed memory cell performance. HSPICE simulation results has confirmed that the proposed structure offers about 34%, 54% and 95% power saving in hold mode, read mode and write mode respectively. In speed and energy point of view it provides about 97% read delay, 92% write delay and 98% energy savings than the conventional memory structures. These results make it clear that the proposed SRAM is suitable for the 5G networks where circuit speed, power and energy consumption are the major concern.

Abstract Rapid advancements in micro-machining and microelectronics over the last few years have accelerated the growth of implanted medical devices that greatly improve a person's life. These devices first gather the signals from different nodes in/on the body, and then, they condition, multiplex, and digitize the signals. Thus, an analog-to-digital converter (ADC), which must continuously convert a variety of analog electrophysiological signals to digital codes, is one of the most crucial and power-hungry components. For implantable medical devices, the successive approximation register (SAR) ADC is a good choice. In this paper, a low-power single-ended SAR ADC architecture is proposed to offer good compromises between power efficiency, conversion accuracy, and design complexity. The proposed architecture supports 8-bit resolution at a sampling rate of 1 MS/s. Using a 130-nm CMOS process with 1.2 V supply voltage, an effective number of bits (ENOB) of 7.3 dB is achieved while 28.5 μW power is consumed. The ADC core only occupies an active area of about 197 μm × 377 μm.

A novel Gm-C structure of a second-order continuous-time filter is proposed that allows for the independent control of the filter's natural frequency (ω0) and quality factor (Q). The structure consists of two capacitors and four transconductors. Two transconductors together with the capacitors form a lossless second-order circuit with tunable ω0. The other two transconductors form a variable gain amplifier (VGA) which realizes an adjustable loss and thereby adjustable Q. The proposed solution can be used to implement low-voltage and low-power tunable front-end filter banks for fully integrated CMOS cochlear implants and edge intelligence accelerators. An example filter bank powered by 0.5 V and consuming 40 nW of power per single filter is designed and simulated using a 180 nm CMOS process. Circuitries for the adaptive control of transistor bias at a reduced supply voltage are proposed. The ω0 and Q control circuitries are also proposed: a delay-locked loop (DLL)-based system for fine ω0 tuning and a binary-weighted current mirror for Q adjustment. The proposed solution allows for the independent regulation of ω0 and Q within the ranges of 0.25–8 kHz and 1–14, respectively, with a relative tolerance of up to 5% across a filter bank. [ABSTRACT FROM AUTHOR]

Abstract—This article describes the step-by-step design and implementation of a GaAs power amplifier (PA) that operates at low voltage and low power, while providing broadband coverage. The design methodology used to ensure high performance within the desired frequency range is explained in detail, and the matching network and bias circuit are implemented using microstrip technology. A PA prototype is then fabricated to demonstrate the performance of the proposed design, using the Agilent Technologies (hp)® ATF13786 field effect transistor. The evaluation of the PA's performance involves the application of both small-signal and large-signal measurements. Notably, large-signal assessments reveal a power gain of 10 dB, a saturated output power of 15.8 dBm, power-added efficiency (PAE) of 21.8%, and drain efficiency (DE) of 26.3% at a frequency of 3.5 GHz. This design, characterized by its simplicity, compactness, and versatility, exhibits applicability across a diverse array of contexts. [ABSTRACT FROM AUTHOR]

In this study, a two-dimensional electron gas (2DEG), which is a conductive layer formed at the interface of Al2O3 and TiO2, was used as an electrode for resistive random access memory (RRAM) and implemented in a cell size down to 30 nm. For an RRAM device comprising W/2DEG/TiO2/W, we confirmed that the dominant switching mechanism changed from interfacial to filamentary as the cell size decreased from 500 nm to 30 nm. Through analyses of changes in forming characteristics and conduction mechanisms in the low resistive state depending on the cell size, it was identified that the 2DEG acted as an oxygen-scavenging layer of TiO2 during the resistive switching process. By comparing the switching characteristics of RRAM devices with and without 2DEG for a 30 nm cell size, we confirmed that a high-performance 2DEG RRAM was realized, with highly uniform current–voltage characteristics, a low operating voltage (∼1 V), and a high on/off ratio (>102). Finally, the applicability of the proposed device to a crossbar array was validated by evaluating 1S1R operation with an NbO2-based selector. Considering the improved switching uniformity, the 2DEG RRAM shows promise for high-density memory applications. [ABSTRACT FROM AUTHOR]

AbstractOver the past 25 years, the average cadence of National Aeronautics and Space Administration (NASA) missions that employ radioisotope thermoelectric generators (RTGs) or other radioisotope power systems (RPSs) is approximately one per decade. Currently, the only flight-qualified RPS in the NASA inventory for space power applications is the multi-mission RTG, which has a beginning-of-life (BOL) power output of approximately 120 W(electric). In addition, NASA and the U.S. Department of Energy also manage the Next Generation Radioisotope Thermoelectric Generator Development Project, with a projected BOL power of around 245 W(electric).However, if a lower-power RPS unit was available, would there be sufficient mission pull to increase the cadence of RPS-powered missions? We believe the answer to this question is yes, which drove the evolution of a concept study that examines the feasibility of a low-power RPS based on a single general purpose heat source (GPHS) that could be developed rapidly with low risk and cost. This paper discusses the results of a concept study of an RPS system that utilizes novel ruggedized silicon germanium thermoelectric modules with a projected BOL power of 15 W(electric).This new RTG design could help enable a new class of low-powered space exploration missions for NASA, the European Space Agency, or commercial applications. In addition, this paper addresses the next steps required to evolve the concept beyond its current status to conceptual design. [ABSTRACT FROM AUTHOR]

Summary Nanopore ion channels are a promising solution for certain molecular structure analyses. Large arrays of nanopore channels and their associated readout circuits are used in many molecular studies such as DNA sequencing. Readout circuits must meet challenging performance criteria such as low noise operation, low power consumption, in‐channel digitization capability, and high linearity. Previously, sigma–delta modulators have been presented to address these criteria; however, their specifications show drifts with temperature. In this paper, an approach is presented to keep modulator performance constant with temperature variations. For this purpose, the sigma–delta modulator's feedforward and feedback branches are modified so that their gain coefficient remains constant over a certain temperature range. With large sensors arrays, solutions employing high bias currents in the feedback paths are not suitable due to power consumption limitations. Here, the design gives the possibility of switching low current levels in the feedback paths without affecting the ENOB. The proposed temperature compensation solution shows good performance when temperature is swept from 27°C to 100°C. Over the mentioned temperature range, the gain and bandwidth of the modulator show a change of less than 0.4%. It is further shown that for a 10 kHz input current signal with an amplitude of 600 pA, the ENOB and power consumption are 12.9 and 4.6 mW, respectively. [ABSTRACT FROM AUTHOR]

An ultra-low quiescent current output-capacitor-less low dropout (OCL-LDO) regulator for power-sensitive applications is proposed in this paper. To improve the gain of the OCL-LDO feedback loop, the error amplifier employs a combination of a cross-coupled input stage for boosting the equivalent input transconductance and a negative resistance technique to improve the gain. Meanwhile, in order to address the issue of transient response of the ultra-low quiescent current OCL-LDO, a sub-threshold slew-rate enhancement circuit is proposed in this paper, which consists of a transient signal input stage and a slew-rate current increase branch. The proposed OCL-LDO is fabricated in a 0.18 μ m CMOS process with an effective area of 0.049 mm2. According to the measurement results, the proposed OCL-LDO has a maximum load current of 100 mA and a minimum quiescent current of 640 nA at an input voltage of 1.2 V and an output voltage of 1 V. The overshoot and undershoot voltages are 197 mV and 201 mV, respectively, and the PSR of the OCL-LDO is −72.4 dB at 1 kHz when the load current is 100 μ A. In addition, the OCL-LDO has a load regulation of 7.6 μ V/mA and a line regulation of 0.87 mV/V. [ABSTRACT FROM AUTHOR]

The lower power object detection challenge (LPODC) at the IEEE/ACM Design Automation Conference is a premier contest in low-power object detection and algorithm (software)-hardware co-design for edge artificial intelligence, which has been a success in the past five years. LPODC focused on designing and implementing novel algorithms on the edge platform for object detection in images taken from unmanned aerial vehicles (UAVs), which attracted hundreds of teams from dozens of countries to participate. Our team SEUer has been participating in this competition for three consecutive years from 2020 to 2022 and obtained sixth place respectively in 2020 and 2021. Recently, we achieved the championship in 2022. In this paper, we presented the LPODC for UAV object detection from 2018 to 2022, including the dataset, hardware platform, and evaluation method. In addition, we also introduced and discussed the details of methods proposed by each year’s top three teams from 2018 to 2022 in terms of network, accuracy, quantization method, hardware performance, and total score. Additionally, we conducted an in-depth analysis of the selected entries and results, along with summarizing representative methodologies. This analysis serves as a valuable practical resource for researchers and engineers in deploying the UAV application on edge platforms and enhancing its feasibility and reliability. According to the analysis and discussion, it becomes evident that the adoption of a hardware-algorithm co-design approach is paramount in the context of tiny machine learning (TinyML). This approach surpasses the mere optimization of software and hardware as separate entities, proving to be essential for achieving optimal performance and efficiency in TinyML applications. [ABSTRACT FROM AUTHOR]

This study explores the potential of converting domestic graywater into electrochemical energy as a sustainable energy solution amidst growing environmental concerns. Employing a custom-designed galvanic cell prototype, the research aims to transform the chemical energy in graywater into electrical energy through redox reactions, quantifying the electrical potential generated. Results demonstrate the prototype's success in generating an average no-load voltage of 5.1907 volts, effectively powering low-power devices like LEDs and validating the viability of greywater as an alternative energy source. However, the study acknowledges limitations such as the prototype's small scale and the potential impact of varied graywater compositions on energy efficiency, suggesting cautious application at larger scales. Future research directions include enhancing prototype efficiency and scalability, understanding the effects of different graywater compositions, and conducting long-term performance assessments. The study contributes to sustainable energy research by offering a novel approach to wastewater energy recovery, promoting environmental sustainability and efficient energy utilization. [ABSTRACT FROM AUTHOR]

The emergence of technologies such as Artificial Intelligence (AI) and the Internet of Things (IoT) has ushered in the era of big data. The demand for low‐power hardware systems and efficient algorithms has become more imperative. In this study, an ultra‐low‐power dynamic memtransistor based on the charge storage junction Field‐Effect Transistor (FET) with a step‐wise potential barrier is developed. A simple yet efficient device structure allows for analog programming and spontaneous relaxation. The device demonstrated fast speed (tens of nanoseconds (ns)) and low current (in picoamperes (pA)), resulting in ultra‐low programming power (in attojoules (aJ)). Furthermore, the device exhibited high reliability, with a 0.4% cycle‐to‐cycle variation and endurance over 107 pulses, owing to its non‐structural destructive operation process. An operation scheme is developed that enables read on/off and program/inhibition mode for 2T (1 memtransistor‐1 selecting transistor) array. The capability to distinguish temporal data using the device's spontaneous relaxation characteristics is demonstrated. A reservoir computing (RC) system framework is constructed using simulation and verified that the dynamic memtransistor can extract features efficiently from a hand‐written digit dataset. It is anticipated that the developed dynamic memtransistor, with its distinctive temporal characteristics, will play a pivotal role in developing a novel low‐power computing framework. [ABSTRACT FROM AUTHOR]

Advanced Encryption Standard (AES) has been a prevalent cryptographic structure in the world. Existing AES-related cryptographic accelerators generally face the problem of high power consumption. To deal with this challenge, this paper presents a cryptographic structure that employs iterative reuse to decrease resource utilization. Through the efficient use of delay-line RAM, the implementation of long-length key storage results in a reduction in the utilization of registers. The computational complexity of AES cryptographic algorithm is reduced by using homomorphic mapping to the inversion operation in S-box from the Galois Fields GF(28) to GF[(24)2]. Such proposed AES cryptographic accelerator is characterized by its low resource utilization and low power consumption. In addition, we have also conducted some simulation analysis to evaluate its performance. The synthesis result indicates that the AES cryptographic accelerator exhibits a 0.74% reduction in utilization of LUT and a 35% decrease in power consumption, as compared to the original version. The proposed AES cryptographic accelerator results in an area of 0.101mm2, a throughput of 12.28Gbps, and a power consumption of 2.56mW in TSMC 90nm. [ABSTRACT FROM AUTHOR]

This paper presents the design of an efficient operational transconductance amplifier (OTA) to be explicitly used for electroencephalogram (EEG) signal acquisition in neural amplifiers (NAs). The central objective of this study revolves around addressing the fundamental compromise between noise and power in the design of NAs. The overarching goal is to effectively mitigate this trade-off by introducing novel approaches. The proposed design's novelty lies in utilizing an adaptive biasing technique instead of the traditional current mirror biasing technique. Furthermore, the conventional input differential pair of the OTA is modified to employ a self cascode flipped voltage follower (SCFVF), which eventually reduces power consumption of the NA to 0.822 μ W. Additionally, notable improvements in noise performance are achieved and found to be 624.9 nV/ (H z) at 1 Hz. The gain and bandwidth range of the input low-noise amplifier is 54.2 dB and 2.8 Hz–207 Hz, respectively, which effectively amplifies low-amplitude noisy incoming signals, addressing the specific requirements of EEG signal acquisition. [ABSTRACT FROM AUTHOR]

This paper introduces an MOS-based intelligent temperature sensor with a linear readout. Compared with similar designs, the proposed sensor utilizes the DIBL effect to reduce the precision requirement for the voltage reference source and compensate for the temperature measurement range. A compact voltage reference circuit is introduced, which generates two reference voltage bases using only three transistors. In addition, the proposed digital readout circuit does not require a subtractor or a divider, further saving area. Fabricated in a 55 nm CMOS process, the proposed sensor occupies a compact area of 3216 μ m 2 . Post-simulation results show it has a maximum error of −0.52/+0.28 °C within the temperature range of −20 °C to 120 °C after two-point calibration. The power supply voltage range of the sensor is 0.8 to 1.8 V. It has a maximum voltage sensitivity of 5.7 °C/V and its power consumption is only 166 nW, with a power supply voltage of 0.8 V. [ABSTRACT FROM AUTHOR]

This paper proposes a low-power charge pump PLL (CPPLL) with 1-V supply voltage in 180-nm CMOS technology, which serves as a low-cost clock generator for heterogeneous integration. Tradeoffs between power consumption, jitter performance and limited loop bandwidth in the conventional CPPLL have been analyzed first, followed by the explanations on reference spur issues in wide bandwidth architectures. A novel two-stage ring oscillator with low voltage capability and linear control gain has been proposed and analyzed in detail, which facilitates the implementation of this 1-V design. Fabricated in SMIC 180-nm technology, the designed PLL occupies a die area of 0.177mm2 with an integrated loop filter. The PLL draws 1.8mA when working at 480MHz, and shows a rms jitter of 7.2pS, which is 20 times more power efficient compared with PLLs with similar frequency and technology node. The design shows potential for heterogeneous integration. [ABSTRACT FROM AUTHOR]

A low power clock generator with self-calibration for UHF RFID tags compatible with the EPCglobal Class-1 Gen-2 (EPC Gen2) standard is presented. By utilizing the timing information of the reader to tag (R ⇒ T) link symbols, the frequency accuracy of the calibrated clock can meet the stringent requirement of the standard. Designed in a 0.18 μ m standard CMOS technology, simulation results show that the frequency error of the clock source is only from − 2.07 to + 1.4% of the target frequency of 2.56 MHz. The power consumption is only 720 nW. [ABSTRACT FROM AUTHOR]

This paper presents a new biquad filter based on carbon nanotube field-effect transistor (CNFET) technology. Implementing various filter modes (high-pass, low-pass, band-pass, and band-stop) in four operating modes (voltage, current, transconductance, and transresistance) with a unified circuit structure is the fundamental feature of the proposed filter. The proposed universal filter is intended for commercial radio communications in the FM band to reduce power consumption and chip area occupation. The proposed circuit can adjust a wide frequency range and thus cover multiple radio channels with minimum noise and distortion on the signal. The proposed filter in 20 nm technology has been simulated using advanced design system (ADS) software to investigate the effects of high-frequency effects. The minimum power consumption is 360 nW, with a supply voltage of 0.9 V, with the ability to independently adjust the center frequency (22 MHz < f0 < 120 MHz) and filter quality factor (0.6 < Q < 23) and the use of grounded capacitors to absorb parasitic effects are among the advantages of the proposed circuit. The proposed Gm-C circuit has the highest figure of merit (FOM) value of 318.5. Moreover, its resistance to process variations, power supply, and temperature changes demonstrates the appropriate performance of the proposed filter. [ABSTRACT FROM AUTHOR]

With the reduction of CMOS technology to nanometric dimensions, it is thought that the end of atomic limits in integrated circuit applications is almost approached and some problems are encountered in production. Carbon nanotube field effect transistors (CNTFETs) are considered a proper option to replace CMOS near term owing to their superior properties such as scalability and better channel electrostatics. For this purpose, a low-voltage, low-power Voltage Differencing Inverting Buffered Amplifier (VDIBA) structure is propose with a 32 nm CNTFET, in this article. The proposed CNTFET VDIBA structure operates with a bias current of 1 µA and consumes 14.32 µW of power with a supply voltage of ± 0.3 V. Compared to the traditional CMOS VDIBA structure, the power consumption is reduced by 733 times. Besides, proposed VDIBA structure has a bandwidth of 43.788 GHz. [ABSTRACT FROM AUTHOR]

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A low‐power multibit delta–sigma modulator (DSM) based on a passive and unattenuated summation scheme is proposed. The summation circuit achieves multiplication of the voltage signal carried on the summation capacitor through a bidirectional sampling technique, thereby compensating for the inherent attenuation caused by passive summation, which eliminates the need for an active operational transconductance amplifier (OTA) to achieve perfect summation. Here, a second‐order DSM based on a 4‐bit first‐order passive noise‐shaping (NS) SAR quantizer is employed to satisfy the SNDR requirements exceeding 100 dB, which validates the reliability of the summation scheme. In addition, a cascoded floating inverter amplifier (FIA) is used as the core OTA to further improve system energy efficiency. Simulation results demonstrate that at a supply voltage of 1.2 V and a bandwidth of 20 kHz, the SNDR reaches 102.62 dB, power consumption is only 148.32 μW, and the Schreier figure‐of‐merit (FoM) of the SNDR is 183.92 dB. The results demonstrate that the proposed DSM has considerable potential for widespread application in the audio domain. [ABSTRACT FROM AUTHOR]

Rapid advancements in micro-machining and microelectronics over the last few years have accelerated the growth of implanted medical devices that greatly improve a person's life. These devices first gather the signals from different nodes in/on the body, and then, they condition, multiplex, and digitize the signals. Thus, an analog-to-digital converter (ADC), which must continuously convert a variety of analog electrophysiological signals to digital codes, is one of the most crucial and power-hungry components. For implantable medical devices, the successive approximation register (SAR) ADC is a good choice. In this paper, a low-power single-ended SAR ADC architecture is proposed to offer good compromises between power efficiency, conversion accuracy, and design complexity. The proposed architecture supports 8-bit resolution at a sampling rate of 1 MS/s. Using a 130-nm CMOS process with 1.2 V supply voltage, an effective number of bits (ENOB) of 7.3 dB is achieved while 28.5 μW power is consumed. The ADC core only occupies an active area of about 197 μm × 377 μm. [ABSTRACT FROM AUTHOR]

In the face of rising population, erratic climate, resource depletion, and increased exposure to natural hazards, environmental monitoring is increasingly important. Satellite data form most of our observations of Earth. On-the-ground observations based on in situ sensor systems are crucial for these remote measurements to be dependable. Providing open-source options to rapidly prototype environmental datalogging systems allows quick advancement of research and monitoring programs. This paper introduces Loom, a development environment for low-power Arduino-programmable microcontrollers. Loom accommodates a range of integrated components including sensors, various datalogging formats, internet connectivity (including Wi-Fi and 4G Long Term Evolution (LTE)), radio telemetry, timing mechanisms, debugging information, and power conservation functions. Additionally, Loom includes unique applications for science, technology, engineering, and mathematics (STEM) education. By establishing modular, reconfigurable, and extensible functionality across components, Loom reduces development time for prototyping new systems. Bug fixes and optimizations achieved in one project benefit all projects that use Loom, enhancing efficiency. Although not a one-size-fits-all solution, this approach has empowered a small group of developers to support larger multidisciplinary teams designing diverse environmental sensing applications for water, soil, atmosphere, agriculture, environmental hazards, scientific monitoring, and education. This paper not only outlines the system design but also discusses alternative approaches explored and key decision points in Loom's development. [ABSTRACT FROM AUTHOR]

We demonstrate a low-power (Pdc) 25.5–30.7 GHz CMOS variable-gain amplifier (VGA). The VGA constitutes a common-source (CS) input stage (M1), followed by current-reused CS gain (M2) and output stages (M3). Transistors M1-M3 adopt the topology of B-to-D with RB, i.e., body terminal is connected to drain via a large resistance RB, for body self-forward-bias and floating (BSFBF). This leads to gain boosting and NF reduction of the VGA at the same Pdc due to larger transconductance gm (because of larger bias current) and smaller bias voltage, and effective suppression of the substrate leakage and noise. Simultaneous input and noise matching are achieved by suitable selection of the size and bias of M1, and the inductance of Lg1 and L1. Analog switch transistor M4 is in parallel with M3 to tune its overdrive (VOV) and drain-source voltage (VDS) for fine tuning of S21. Digital switch transistor M5 (in conjunction with the series coupling capacitance CC and resonant inductance L10) is in parallel with M2 to control its AC VDS for coarse tuning of S21. In the case of M5 being turned-on, the series of CC-M5-L10 is close to a short-circuit (~ 4.6 Ω) at the output node of M2 over the 3-dB gain bandwidth (f3dB) of 18.4–30.7 GHz. This leads to S21 tuning range boosting. Moreover, M4-M5 adopt DTMOS with RB, i.e., body of M4-M5 is connected to gate via RB, for BSFBF to lower the on-state channel resistance (Rch) and increase the off-state Rch. Further S21 tuning range boosting is attained. The VGA consumes 9 mW, and achieves S21 of 15.4 ± 1.5 dB for 18.4–30.7 GHz, tuning range of 29.8 dB (15.5 ~ − 14.3 dB) at 28 GHz, average NF (NFavg) of 2.79 dB for 18–31 GHz, and figure-of-merit (FOM) of 2.24 GHz. The NFavg and FOM are one of the best results ever reported for wideband VGAs/LNAs with Pdc lower than 10 mW. The eminent results of the VGA indicate it is suitable for 28 GHz 5G systems. [ABSTRACT FROM AUTHOR]

Counter circuits play a crucial role in Modified Booth Wallace (MBW) tree multiplier architectures, serving as fundamental partial product accumulation circuits. In this paper, we propose a novel architecture for a low-power 7:3 counter based on hybrid full adders (HFAs). Two new designs of HFAs are introduced to realize this counter, enabling the implementation of a 7:3 counter with only 54 transistors. Simulation results demonstrate that the proposed HFA-based 7:3 counter architecture consumes a power of 22.6 µW with a latency of 305 ps, showcasing significant improvements in power-delay-product compared to state-of-the-art designs. [ABSTRACT FROM AUTHOR]

The logical effort method is a technique for accurately estimating the delay of a CMOS circuit. This method is computed as a ratio of capacitances. In this work we propose a low-power full adder circuit and compare it with three established low power full adder circuits. The circuits were designed utilizing Cadence Virtuoso software and GPDK 45nm technology. A comparison was conducted based on delay, average power, power delay product, and transistor count. In this work, all circuits are resized to achieve minimum delay according to the logical effort. It has been shown that the proposed design (design 4) is showing better performance in terms of average power, delay of sum and delay of carry than other designs by 34.23%, 26.81%, and 4.33%, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a field stack lighting (FSL) driving method and develops an OLED‐on‐silicon microdisplay with low power. By modulating subfield luminance across time and magnitude, FSL generates linear weights. Compared to the pulse width modulation (PWM), FSL achieves a power reduction of 39.33% and enhances OLED lifetime by 4.2 times. In contrast to analog amplitude modulation (AAM), minimum power reduction of FSL is noted to be 57.15%. [ABSTRACT FROM AUTHOR]

Dual gate device with mobility of 20cm2/Vs has been applied to improve power consumption of oxide products, the devices show high on‐state current of more than 45uA, good uniformity of ΔVth 1.03V, PBTS of 2.18V. The optimized pixel design of 14inch WQXGA achieves high aperture ratio of 74% and transmittance of over 9.5%. This 120Hz demo with brightness of 150nit can significantly reduce power consumption by 65%, from 2.1W to 1.27W. [ABSTRACT FROM AUTHOR]