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Data centers are a vital and fundamental infrastructure component of the cloud. The requirement to execute a large number of demanding jobs places a premium on processing capacity. Parallelizing jobs to run on multiple cores reduces execution time. However, there is a decreasing marginal benefit to using more cores, with the speedup function quantifying the achievable gains. A critical performance metric is flow time. Previous results in the literature derived closed-form expressions for the optimal allocation of cores to minimize total flow time for a power-law speedup function if all jobs are present at time 0. However, this work did not place a constraint on the makespan. For many diverse applications, fast response times are essential, and latency targets are specified to avoid adverse impacts on user experience. This paper is the first to determine the optimal core allocations for a multicore system to minimize total flow time in the presence of a completion deadline (where all jobs have the same deadline). The allocation problem is formulated as a nonlinear optimization program that is solved using the Lagrange multiplier technique. Closed-form expressions are derived for the optimal core allocations, total flow time, and makespan, which can be fitted to a specified deadline by adjusting the value of a single Lagrange multiplier. Compared to the unconstrained problem, the shortest job first property for optimal allocation is maintained; however, a number of other properties require revising and other properties are only retained in a modified form (such as the scale-free and size-dependence properties). It is found that with a completion deadline the optimal solution may contain groups of simultaneous completions. In general, all possible patterns of single- and group-completion need to be considered, producing an exponential search space. However, the paper determines analytically that the optimal completion pattern consists of a sequence of single completions followed by a single group of simultaneous completions at the end, which reduces the search space dimension to being linear. The paper validates the Lagrange multiplier approach by verifying constraint qualifications. [ABSTRACT FROM AUTHOR]

The interdisciplinary aspect in the study of the core concept in complex genetically organized systems of natural and anthropogenic origin is analyzed. The purpose of the article is scientific substantiation of the nature and essence of the genetic core of the electromechanical system. Based on the provisions of the theory of genetic evolution of electromechanical systems, the information essence of the genetic core as a carrier of genetic information of the primary source of the electromagnetic field is revealed. The analysis of the invariant relationships of the genetic nucleus with the structure of groups, subgroups and small periods, the generative system was carried out. An invariant connection between the core concept and the processes of evolutionary speciation and the main taxonomic categories of electromechanical systems has been established. Based on the results of the system-genetic analysis, a definition of the concept of the genetic core is proposed. The relationship between genetic and energy cores in the hierarchy of levels of complexity of electromechanical systems is studied. The principles of genetic structuring of complex systems of the multinuclear type are revealed. According to the results of the system-genetic analysis of the conception of the genetic core of electro-mechanical systems, its main properties are summarized. The importance of the obtained research results for the spread of genetic prediction technology and interdisciplinary synthesis to complex electromechanical complexes with nuclei of different physical nature is emphasized. [ABSTRACT FROM AUTHOR]

High-performance computing (HPC) systems need to handle ever-increasing data sizes for fast processing and quick response times. However, modern processors’ caches are unable to handle massive amounts of data, leading to significant cache miss penalties that affect performance. In this context, selecting an effective cache replacement policy is crucial to improving HPC performance. Existing cache replacement policies fall short of Bélády’s optimal algorithm, and we propose a new approach that leverages the coherence state and sharers’ bit-vector of a cache block to make better decisions. We suggest a reinforcement learning-based strategy that learns from past eviction decisions and applies this knowledge to make better decisions in the future. Our approach uses a next-attempt method that combines the results from classic cache replacement algorithms with reinforcement learning. We evaluated our approach using the Sniper simulator and seven kernels from CAP Benchmarks. Our results show that our approach can significantly reduce the cache miss rate by 41.20% and 27.30% in L1 and L2 caches, respectively. In addition, our approach can improve the IPC by 27.33% in the best case and reduce energy consumption by 20.36% compared to an unmodified policy.

This paper proposes, implements, and verifies a multicore real-time scheduler (MCRT scheduler) for periodic and sporadic threads and processes, and non-real-time processes where periodic and sporadic (or event-driven) processes are processed according to real-time characteristics such as limited periods and deadlines. Using the Xenomai and Linux operating systems, the proposed MCRT scheduler was implemented and verified through various test cases designed for multicore operations. The proposed MCRT scheduler generates scheduling tables for periodic and sporadic threads and processes, based on which they are executed during the basic period. The MCRT scheduler was verified using several examples. [ABSTRACT FROM AUTHOR]

Specific and sustained release of nutrients from capsules to the gastrointestinal tract has attracted many attentions in the field of food and drug delivery. In this work, we reported a monoaxial dispersion electrospraying-ionotropic gelation technique to prepare multicore millimeter-sized spherical capsules for specific and sustained release of fish oil. The spherical capsules had diameters from 2.05 mm to 0.35 mm with the increased applied voltages. The capsules consisted of uniform (at applied voltages of ≤ 10 kV) or nonuniform (at applied voltages of > 10 kV) multicores. The obtained capsules had reasonable loading ratios (9.7 %−6.3 %) due to the multicore structure. In addition, the obtained capsules had specific and sustained release behaviors of fish oil into the small intestinal phase of in vitro gastrointestinal tract and small intestinal tract models. The simple monoaxial dispersion electrospraying-ionotropic gelatin technique does not involve complicated preparation formulations and polymer modification, which makes the technique has a potential application prospect for the fish oil preparations and the encapsulation of functional active substances in the field of food and drug industries.

The speed difference between high-performance CPUs and energy-efficient CPUs, which are found in asymmetric performance multicore processors, affects the current form of Amdahl’s law equation. This paper proposes two updates to that equation based on the performance evaluation results of a simple parallel pi program written with OpenCilk. Performance evaluation was done by measuring execution time and instructions per cycle (IPC). The performance evaluation of the parallel program executed on the Intel Core i5 1240P processor did not indicate decreased performance due to asymmetric performance. Instead, the program with efficient work-stealing advantages from OpenCilk performed well. In the case of using the execution time of the P-CPU as a reference to obtain speedup, the evaluation results in a sublinear speedup. Conversely, in the case of using the execution time of the E-CPU as a reference, the evaluation results in a superlinear speedup. This paper proposes two updates to Amdahl’s law equation based on these two evaluation results.

Currently, there are around 4.95 billion people who use the internet, which creates a large audience with an increasing demand for activities that can be done online. Some examples of these activities include social networking, information sharing, and online shopping. Therefore, there is an urgent need for improved levels of secrecy and privacy. It has recently come to light that one of the most serious challenges to the mainstream adoption of business apps is that of online fraud. As a direct consequence of this, issues pertaining to authentic cation, authorization, and identification have emerged as critical considerations in today's open and accessible society. The act of recognizing an entity, whether it be a human, a computer, or a software program, is referred to as the identification process. Authentication and authorization are complementary processes that are used in security systems to decide which persons are permitted to access information resources over a network. Authentication is performed by the user's device, while authorization is performed by the security system. However, a variety of potential solutions have been suggested, one of which is the use of parallelism in order to boost the efficiency of authentication methods. This work proposes a new message authentication algorithm that is applied in parallel over a multicore processor. The proposed message authentication algorithm uses two PNGRs and two substitution boxes to encrypt and authenticate the plain message. The encryption process has a one-round operation, making it a fast technique to encrypt and decrypt blocks of messages. In comparison to the existing method, the proposed authentication method outperforms the parallel speck-based authentication method by an average of 3.27 times faster when executed over a multicore CPU. The average speedup compared to the sequential version of the proposed algorithm and its parallel implementation is 2.99. The proposed method passes the most difficult randomness test, and the obtained MAC values are tested further to meet other security measurements. [ABSTRACT FROM AUTHOR]

Autonomous multicopters often feature federated architectures, which incur relatively high communication costs between separate hardware components. These costs limit the ability to react quickly to new mission objectives. Additionally, federated architectures are not easily upgraded without introducing new hardware that impacts size, weight, power and cost constraints. In turn, such constraints restrict the use of redundant hardware to handle faults. In response to these challenges, we propose FlyOS, an Integrated Modular Avionics approach to consolidate mixed-criticality flight functions in software on heterogeneous multicore aerial platforms. FlyOS is based on a separation kernel that statically partitions resources among virtualized sandboxed OSes. We present a dual-sandbox prototype configuration, where timing- and safety-critical flight control tasks execute in a real-time OS alongside mission-critical vision-based navigation tasks in a Linux sandbox. Low latency shared memory communication allows flight commands and data to be relayed in real-time between sandboxes. A hypervisor-based fault-tolerance mechanism is also deployed to ensure failover flight control in case of critical function or timing failures. We validate FlyOS's performance and showcase its benefits when compared against traditional architectures in terms of predictable, extensible and efficient flight control. [ABSTRACT FROM AUTHOR]

Virtualization has become one of the main tools for making efficient use of the resources offered by multicore embedded platforms. In recent years, even sectors such as space, aviation, and automotive, traditionally wary of adopting this type of technology due to the impact it could have on the safety of their systems, have been forced to introduce it into their day-to-day work, as their applications are becoming increasingly complex and demanding. This article provides a comprehensive review of the research work that uses or considers the use of a hypervisor as the basis for building a virtualized safety-critical embedded system. Once the hypervisors developed or adapted for this type of system have been identified, an exhaustive qualitative comparison is made between them. an exhaustive qualitative comparison is made between them. To the best of our knowledge, this is the first time that all this information is collected in a single article. Therefore, the main contribution of this article is that it collects and categorizes the information of each hypervisor and compares them with each other, so that this article can be used as a starting point for future researchers in this area, who will be able to quickly check which hypervisor is best suited to their research needs.

The need to ensure the longevity of Wireless Sensor Networks (WSNs) and secure their communication has spurred various researchers to come up with various WSN models. Prime among the methods for extending the life span of WSNs is the clustering of Wireless Sensors (WS), which reduces the workload of WS and thereby reduces its power consumption. However, a drastic reduction in the power consumption of the sensors when multicore sensors are used in combination with sensors clustering has not been well explored. Therefore, this work proposes a WSN model that employs clustering of multicore WS. The existing Elliptic Curve Cryptographic (ECC) algorithm is optimized for parallel execution of the encryption/decryption processes and security against primitive attacks. The Elliptic Curve Diffie-Helman (ECDH) was used for the key exchange algorithm, and the Elliptic Curve Digital Signature Algorithm (ECDSA) was used to authenticate the communicating nodes. Security analysis of the model and comparative performance analysis with the existing ones were demonstrated. The security analysis results reveal that the proposed model meets the security requirements and resists various security attacks. Additionally, the projected model is scalable, energy-conservative, and supports data freshness. The results of comparative performance analysis show that the proposed WSN model can efficiently leverage multiprocessors and/or many cores for quicker execution and conserves power usage.

Domain Adaptation (DA) is a technique that aims at extracting information from a labeled remote sensing image to allow classifying a different image obtained by the same sensor but at a different geographical location. This is a very complex problem from the computational point of view, specially due to the very high-resolution of multispectral images. TCANet is a deep learning neural network for DA classification problems that has been proven as very accurate for solving them. TCANet consists of several stages based on the application of convolutional filters obtained through Transfer Component Analysis (TCA) computed over the input images. It does not require backpropagation training, in contrast to the usual CNN-based networks, as the convolutional filters are directly computed based on the TCA transform applied over the training samples. In this paper, a hybrid parallel TCA-based domain adaptation technique for solving the classification of very high-resolution multispectral images is presented. It is designed for efficient execution on a multi-node computer by using Message Passing Interface (MPI), exploiting the available Graphical Processing Units (GPUs), and making efficient use of each multicore node by using Open Multi-Processing (OpenMP). As a result, an accurate DA technique from the point of view of classification and with high speedup values over the sequential version is obtained, increasing the applicability of the technique to real problems. [ABSTRACT FROM AUTHOR]

This paper investigates the exploitation of heterogeneous DVFS (dynamic voltage frequency scaling) control for improving the energy efficiency of data-parallel applications on ccNUMA shared-memory systems. We propose to adjust the clock frequency individually for the appropriately selected groups of cores, taking into account the diversified costs of parallel computation. This paper aims to evaluate the proposed approach using two different data-parallel applications: solving the 3D diffusion problem, and MPDATA fluid dynamics application. As a result, we observe the energy-savings gains of up to 20 percentage points over the traditional homogeneous frequency scaling approach on the server with two 18-core Intel Xeon Gold 6240. Additionally, we confirm the effectiveness of our strategy using two 64-core AMD EPYC 7773X. This paper also introduces two pruning algorithms that help select the optimal heterogeneous DVFS setups taking into account the energy or performance profile of studied applications. Finally, the cost and efficiency of developed algorithms are verified and compared experimentally against the brute-force search. • Heterogeneous DVFS method for energy efficiency of regular data-parallel applications. • Individually adjusting clock frequency for cores based on workload distribution. • Pruning algorithms for selecting optimal heterogeneous DVFS setups. [ABSTRACT FROM AUTHOR]

Parallel hierarchical scheduling of multicore processors in avionics hypervisor is being studied. Parallel hierarchical scheduling utilizes modular reasoning about the temporal behavior of the upper Virtual Machine (VM) by partitioning CPU time. Directed Acyclic Graphs (DAGs) are used for modeling functional dependencies. However, the existing DAG scheduling algorithm wastes resources and is inaccurate. Decreasing the completion time (CT) of DAG and offering a tight and secure boundary makes use of joint-level parallelism and inter-joint dependency, which are two key factors of DAG topology. Firstly, Concurrent Parent and Child Model (CPCM) is researched, which accurately captures the above two factors and can be applied recursively when parsing DAG. Based on CPCM, the paper puts forward a hierarchical scheduling algorithm, which focuses on decreasing the maximum CT of joints. Secondly, the new Response Time Analysis (RTA) algorithm is proposed, which offers a general limit for other execution sequences of Noncritical joints (NC-joints) and a specific limit for a fixed execution sequence. Finally, research results show that the parallel hierarchical scheduling algorithm has higher performance than other algorithms. [ABSTRACT FROM AUTHOR]

We propose a hardware technique for cache coherence over the existing approaches that ensure that shared and less frequently used cache blocks bypass private caches of multiple cores. Furthermore, this manuscript proposes a mechanism to tune the aggressiveness of a data prefetcher. Increased cache hit rate and improved performance have been observed since coherence management and prefetching delays are avoided using the proposed bypassing and thread progress-aware prefetch controlling mechanism. Our approach shows around 19% improvement in cache hit rate and 29% average performance improvement over existing state-of-the-art techniques for Parsec & Splash-2 multithreaded benchmarks. [ABSTRACT FROM AUTHOR]

Snoop-based cache coherence protocols perform well in small-scale systems by enabling low latency cache-to-cache data transfers in just two-hop coherence transactions. However, they are not a scalable alternative as they require frequent broadcast of coherence requests. Token coherence protocols were proposed to improve the scalability of snoop-based protocols by removing a large amount of traffic due to broadcast responses. Still, broadcasting coherence requests on every cache miss represents a scalability issue for medium and large-scale systems. In this paper, we propose to reduce the number of broadcast operations in Token coherence protocols by performing an efficient fine-grain private-shared data classification and disabling broadcasts for misses to data classified as private. Our fine-grain classification is orchestrated and stored by the Translation Look-aside Buffers (TLBs), where entries are kept for a longer time than in local caches. We explore different classification granularity accounting for different storage overheads and their impact on filtering coherence traffic. We evaluate our proposals on a set of parallel benchmarks through full-system cycle-accurate simulation and show that a subpage-grain classification offers the best trade-off when accounting for storage, traffic, and performance. When running a 16-core configuration, our subpage-grain classification eliminates 40.1% of broadcast operations compared to not performing any classification and 13.7% of broadcast operations more than a page-grain data classification. This reduction translates into less network traffic (16.0%), and finally, performance improvements of 12.0% compared to not having a classification mechanism. • Evaluation of TLB-based private/shared classification with varying granularities. • Proposal of a new TLB-based sub-page classification mechanism. • Integration of classification techniques to filter Token coherence traffic. • Reduction in traffic by 16% and performance by 20% with a low storage cost. [ABSTRACT FROM AUTHOR]

The article analyzes information security strategies, such as a strategic cooperative game of chicken, balancing business incentives and striving for brinkmanship, and ensuring sufficient security with minimal effort for customers and consumers while not impairing—and in some cases improving—the privacy of their infrastructure and the Internet of Things (IoT) security maturity model (SMM). The benefits of the latter strategy are estimated by selecting an architecture with the core of the IoT SMM in the form of a hierarchy of security practices. Algorithms ensuring privacy and protection from threats are analyzed. A methodology for analyzing and selecting the best architecture for multicore hierarchical clustering of computer systems is proposed. An expert system based on the on-chip MCNPAoC SBIS 1879BM8Y instrument module MS 127.05 with the proposed user interface is implemented. [ABSTRACT FROM AUTHOR]

Automatic differentiation (AD) is a well-known technique for evaluating analytic derivatives of calculations implemented on a computer, with numerous software tools available for incorporating AD technology into complex applications. However, a growing challenge for AD is the efficient differentiation of parallel computations implemented on emerging manycore computing architectures such as multicore CPUs, GPUs, and accelerators as these devices become more pervasive. In this work, we explore forward mode, operator overloading-based differentiation of C++ codes on these architectures using the widely available Sacado AD software package. In particular, we leverage Kokkos, a C++ tool providing APIs for implementing parallel computations that is portable to a wide variety of emerging architectures. We describe the challenges that arise when differentiating code for these architectures using Kokkos, and two approaches for overcoming them that ensure optimal memory access patterns as well as expose additional dimensions of fine-grained parallelism in the derivative calculation. We describe the results of several computational experiments that demonstrate the performance of the approach on a few contemporary CPU and GPU architectures. We then conclude with applications of these techniques to the simulation of discretized systems of partial differential equations. [ABSTRACT FROM AUTHOR]

This survey reviews the scientific literature on techniques for reducing interference in real-time multicore systems, focusing on the approaches proposed between 2015 and 2020. It also presents proposals that use interference reduction techniques without considering the predictability issue. The survey highlights interference sources and categorizes proposals from the perspective of the shared resource. It covers techniques for reducing contentions in main memory, cache memory, a memory bus, and the integration of interference effects into schedulability analysis. Every section contains an overview of each proposal and an assessment of its advantages and disadvantages.

Dalam membangun sebuah laboratorium keamanan informasi, perlu diperhatikan aspek perangkat, aplikasi, dan lingkungannya (environment). Laboratorium keamanan informasi ini bertujuan untuk menguji tingkat keamanan dari sebuah aplikasi yang akan atau sudah dibangun. Tetapi yang menjadi masalah utama adalah sulitnya pemilihan jenis perangkat keras yang sesuai dengan kebutuhan. Ada beberapa parameter yang harus diperhatikan dalam menentukan komponen perangkat keras yang tepat, yaitu Random Access Memeory (RAM), Processor, dan Network Interface Card (NIC). Dalam penelitian ini, hanya berfokus pada pengujian pengaruh Multi Core dalam sebuah Processor. Seperti yang diketahui, Processor merupakan perangkat utama yang sangat penting dalam komputer. Jika diibaratkan, Processor merupakan otak dari komputer yang akan digunakan untuk menguji tingkat keamanan dari sebuah aplikasi yang akan atau sudah dibangun. Selain itu, pemilihan jenis Processor juga sangat berpengaruh dalam pemrosesan tugas yang akan dilakukan oleh komputer uji dalam rancangan pembangunan laboratorium kemanan informasi ini, sehingga pemilihan Processor sangatlah penting. Hasil akhir dari penelitian ini adalah untuk mendapatkan rekomendasi Processor yang sesuai dengan kebutuhan komputer uji pada Blueprint laboratorium kemanan informasi

The demand for heterogeneous multicore platforms is growing at a rapid pace in modern gadgets. Such platforms help cater to various types of applications and thus provide high resource utilization. As each task has a different execution time on different types of cores, it is very challenging to schedule tasks on such platforms. With the advancement in technology, it has become imperative to manage energy consumption and temperatures of cores in multicore platforms. Hence, in this work, we propose RT-SEAT, a hybrid real-time scheduler for energy and temperature-efficient heterogeneous multicore systems. Through extensive experimental analysis, we have found that RT-SEAT is able to schedule more tasks (up to 46.75%), save more energy (up to 6.89%), and reduce the average temperature of the cores by 20.45%, when the system workload varies from 50% to 100%, with respect to the state-of-the-art.

In this letter, low-phase-nose multicore class-F voltage-controlled oscillators (VCOs) using coupled-lined-based synchronization topology are proposed. Compared to traditional resistance-coupled multicore VCOs, the proposed coupled-line-based topology improves the $Q$ of the small inductors in the millimeter-wave frequency range. Mode ambiguity is eliminated for a robust oscillation startup. Quad-core and oct-core VCO prototypes are designed and implemented in 65-nm CMOS process, which exhibit a measured frequency tuning range of 20.5% centered at 31.32 GHz. The quad-core VCO has a measured phase noise (PN) of −134.33 dBc/Hz and a corresponding FoM of 191.32 dBc/Hz at 10-MHz offset from 28.28 GHz. The oct-core VCO has a measured PN of −137.23 dBc/Hz and a corresponding FoM of 191.08 dBc/Hz at 10-MHz offset from 28.16 GHz. [ABSTRACT FROM AUTHOR]

The security of many public key cryptosystems that are used today depends on the difficulty of factoring an integer into its prime factors. Although there is a polynomial time quantum-based algorithm for integer factorization, there is no polynomial time algorithm on a classical computer. In this paper, we study how to improve the wheel factoring method using two approaches. The first approach is introducing two sequential modifications on the wheel factoring method. The second approach is parallelizing the modified algorithms on a parallel system. The experimental studies on composite integers n that are a product of two primes of equal size show the following results. (1) The percentages of improvements for the two modified sequential methods compared to the wheel factoring method are almost 47 % and 90 % . (2) The percentage of improvement for the two proposed parallel methods compared to the two modified sequential algorithms is 90 % on the average. (3) The maximum speedup achieved by the best parallel proposed algorithm using 24 threads is almost 336 times the wheel factoring method. [ABSTRACT FROM AUTHOR]

In this paper, we identify that memory performance plays a crucial role in the feasibility and effectiveness for performing denial-of-service attacks on shared cache. Based on this insight, we introduce new cache DoS attacks, which can be mounted from the user-space and can cause extreme worst-case execution time (WCET) impacts to cross-core victims—even if the shared cache is partitioned—by taking advantage of the platform’s memory address mapping information and HugePage support. We deploy these enhanced attacks on two popular embedded out-of-order multicore platforms using both synthetic and real-world benchmarks. The proposed DoS attacks achieve up to 111X WCET increases on the tested platforms. [ABSTRACT FROM AUTHOR]