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The current state of affairs in the field of using polymer hydrogels for the creation of innovative systems for signal and image processing, of which computing is a special case, is analyzed. Both of these specific examples of systems capable of forming an alternative to the existing semiconductor-based computing technology, but assuming preservation of the used algorithmic basis, and non-trivial signal converters, the nature of which requires transition to fundamentally different algorithms of data processing, are considered. It is shown that the variability of currently developed information processing systems based on the use of polymers, including polymer hydrogels, leads to the need to search for complementary algorithms. Moreover, the well-known thesis that modern polymer science allows for the realization of functional materials with predetermined properties, at the present stage, receives a new sounding: it is acceptable to raise the question of creating systems built on a quasi-biological basis and realizing predetermined algorithms of information or image processing. Specific examples that meet this thesis are considered, in particular, promising information protection systems for UAV groups, as well as systems based on the coupling of neural networks with holograms that solve various applied problems. These and other case studies demonstrate the importance of interdisciplinary cooperation for solving problems arising from the need for further modernization of signal processing systems. [ABSTRACT FROM AUTHOR]

The current state of affairs in the field of using polymer hydrogels for the creation of innovative systems for signal and image processing, of which computing is a special case, is analyzed. Both of these specific examples of systems capable of forming an alternative to the existing semiconductor-based computing technology, but assuming preservation of the used algorithmic basis, and non-trivial signal converters, the nature of which requires transition to fundamentally different algorithms of data processing, are considered. It is shown that the variability of currently developed information processing systems based on the use of polymers, including polymer hydrogels, leads to the need to search for complementary algorithms. Moreover, the well-known thesis that modern polymer science allows for the realization of functional materials with predetermined properties, at the present stage, receives a new sounding: it is acceptable to raise the question of creating systems built on a quasi-biological basis and realizing predetermined algorithms of information or image processing. Specific examples that meet this thesis are considered, in particular, promising information protection systems for UAV groups, as well as systems based on the coupling of neural networks with holograms that solve various applied problems. These and other case studies demonstrate the importance of interdisciplinary cooperation for solving problems arising from the need for further modernization of signal processing systems.

In this paper, the formulation of Quantum Mechanics in terms of fuzzy logic and fuzzy sets is explored. A result by Pykacz, which establishes a correspondence between (quantum) logics (lattices with certain properties) and certain families of fuzzy sets, is applied to the Birkhoff–von Neumann logic, the lattice of projectors of a Hilbert space. Three cases are considered: the qubit, two qubits entangled, and a qutrit 'nested' inside the two entangled qubits. The membership functions of the fuzzy sets are explicitly computed and all the connectives of the fuzzy sets are interpreted as operations with these particular membership functions. In this way, a complete picture of the standard quantum logic in terms of fuzzy sets is obtained for the systems considered. [ABSTRACT FROM AUTHOR]

Abstract The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or VDD. This way, in a single‐VDD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count.

This paper presents hybrid design of a Ternary Inverter (TI) circuit by integrating an Ovonic-Threshold-Switching (OTS) based Phase-Change-Memory (PCM) cell between Complementary-Metal-Oxide-Semiconductor (CMOS) transistors. Volatile OTS behaviour of the PCM structure helps to generate the ternary state. Reliability of the proposed TI design has been demonstrated through the Monte-Carlo simulations in Cadence-Spectre simulator incorporating both Process and Mismatch variability at all corners. The proposed inverter cell consumes 10.44 $\mu$ W power and 1.47 ns delay on UMC-180 nm technology node. Moreover to demonstrate the scaling potential, we have simulated the proposed inverter at various technology nodes i.e 180/90/65/28 nm. At advanced feature sizes, power and delay are improved by significant amount. For benchmarking, we have compared the proposed TI design with various state-of-the-art hybrid structures. Furthermore, to demonstrate potential applications, we designed and simulated ternary universal logic gates i.e NAND/NOR. Benefits of the proposed TI in circuit applications are shown through a Ternary Multiplier (TMUL) arithmetic circuit implementation. Finally, a Ternary-Static-Random-Access-Memory (TSRAM) is proposed with two back-to-back connected CMOS-PCM TIs with three bit storing capability. [ABSTRACT FROM AUTHOR]

With the miniaturization of digital integrated circuits, electronic systems with increased functionality and enhanced performance are preferred. Multi-valued logic design is a promising alternative that offers a higher number of data/information which leads to energy efficiency, higher information density and reduced circuit overheads in terms of interconnect complexity. Hence in this work multi-valued logic design benefits of increased computational capability and reduced interconnect complexity are being explored for the implementation of sequential elements viz. ternary shift registers. Carbon nanotube field-effect transistors(CNTFETs) unique feature of alteration of threshold voltage by variations in CNT diameter further favor its suitability to implement ternary logic designs. Here single-edge triggered ternary shift registers design methodology is presented using multiplexer based D-flip-flop cells. The design of D-flip-flops is performed using multiplexer based positive and negative latches. After this series connection of D-flip-flop is performed to construct serial input serial output and parallel input serial output registers. The parallel input serial output registers can operate in two modes of loading and shifting and three different configurations of AND-OR logic, NAND logic and latch based selection circuitry are proposed. For performance analysis Synopsis HSPICE simulations are conducted using the 32 nm CNTFET Stanford model. According to simulation results, for the proposed ternary shift registers maximum reduction in power consumption and energy consumption of more than 80% are obtained as compared to recent counterparts. [ABSTRACT FROM AUTHOR]

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In this paper, we suggest an implementation of non-commutative logic and apply its operators for decision-making in a group of autonomous agents. The suggested operators extend the uninorm and absorbing norm aggregators and use an additional asymmetry parameter that defines the "level of non-commutativity". The value of this parameter is specified using the perception bias of humans measured in the experiments. The suggested operators and decision-making method are illustrated by the simulated behavior of mobile robots in the group, which verified the possibility of processing systematic sensing errors, as well as of distinguishing and mimicking the biased decisions. [ABSTRACT FROM AUTHOR]

The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or VDD. This way, in a single‐VDD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count. [ABSTRACT FROM AUTHOR]

In this study, the logic‐in‐memory operations are demonstrated of ternary NAND and NOR logic gates consisting of double‐gated feedback field‐effect transistors. The component transistors reconfigure their operation modes into n‐ or p‐channel modes by adjusting the gate biases. The highly symmetrical operation between these operation modes with an excellent on‐current ratio of 1.03 enables three distinguishable and stable logic levels in the ternary logic gates. Moreover, the ternary logic gates maintain the three logic states for several tens to hundreds of seconds under zero‐bias condition. This study demonstrates that the ternary logic gates are promising candidates for next‐generation low‐power computing systems. [ABSTRACT FROM AUTHOR]

Generalized Rademacher functions, constructed as a sequence of elements of Galois fields are intended to find the spectral representation of signals with levels. These functions form a complete basis on the interval corresponding to -1 discrete time intervals and for passing into the classical Rademacher functions. The advantage of such spectra obtained using Galois Fields Fourier Transform is that the range of variation of the spectrum amplitudes remains the same as the range of variation of the original signal, which is modeled on discrete time functions taking values in the Galois field.

Abstract In this study, the logic‐in‐memory operations are demonstrated of ternary NAND and NOR logic gates consisting of double‐gated feedback field‐effect transistors. The component transistors reconfigure their operation modes into n‐ or p‐channel modes by adjusting the gate biases. The highly symmetrical operation between these operation modes with an excellent on‐current ratio of 1.03 enables three distinguishable and stable logic levels in the ternary logic gates. Moreover, the ternary logic gates maintain the three logic states for several tens to hundreds of seconds under zero‐bias condition. This study demonstrates that the ternary logic gates are promising candidates for next‐generation low‐power computing systems.

Combinations of n- and p-type semiconductors (with thicknesses of a few nanometers or ultrathin) deposited at low temperatures are creating new opportunities for novel devices and circuits. We demonstrate an antiambipolar switch (AAS) device using a heterojunction comprising extremely thin ZnO and Te layers operating at a complementary metal-oxide semiconductor (CMOS)-compatible bias (∼1.2 V) with a high peak-to-valley ratio (∼10 4 ). The entire process was performed at a full wafer scale with a low thermal budget at temperatures below 150 °C. The device count and area of the binary-to-ternary converter designed with this device were reduced by ∼95% and ∼97%, respectively. In addition, we demonstrate a few examples of binary-ternary logic circuits to show that the system complexity and computing efficiency of the binary CMOS architecture can be dramatically improved by easily cointegrating the ZnO-Te AAS-based converter in the back-end-of-line structure.

Multivalued logic (MVL) systems, in which data are processed with more than two logic values, are considered a viable solution for achieving superior processing efficiency with higher data density and less complicated system complexity without further scaling challenges. Such MVL systems have been conceptually realized by using negative transconductance (NTC) devices whose channels consist of van der Waals (vdW) heterojunctions of low-dimensional semiconductors; however, their circuit operations have not been quite ideal for driving multiple stages in real circuit applications due to reasons such as a reduced output swing and poorly defined logic states. Herein, we demonstrate ternary inverter circuits with near rail-to-rail swing and three distinct logic states by employing vdW p-n heterojunctions of single-walled carbon nanotubes (SWCNT) and MoS 2 where the SWCNT layer completely covers the MoS 2 layer. In particular, SWCNTs are inkjet printed to form heterojunctions with MoS 2 grown by chemical vapor deposition (CVD), and both inkjet printing and CVD are fully scalable device fabrication methods for low-dimensional materials. In addition, the NTC characteristics of heterojunction field-effect transistors (H-FETs) are explained based on the electrical characteristics of individual SWCNT and MoS 2 channels. By adjustment of the p-channel characteristics in H-FETs by exploiting the advantages of the inkjet printing technology, the widths of the NTC regions are easily adjusted accordingly. The extended NTC region enables stable middle logic state operations of low-dimensional semiconductors-based ternary inverters over a sufficiently wide input voltage range.

A CMOS ternary logic is demonstrated using a biristor threshold switch (BTS). A biristor, which can operate as a threshold switch, encloses a two-terminal n-p-n structure with a floating p-base region akin to a base-open BJT. The switching mechanism is a single-transistor latch (STL). When a BTS and a MOSFET are serially connected, three stable states are sustained for a ternary logic system. Compared to other ternary devices, static power can be greatly reduced due to low leakage current of the BTS. In addition, the BTS and the MOSFET were co-integrated due to their homeomorphy for fabrication simplicity, i.e., because the BTS has a structure identical to that of a MOSFET, unlike other threshold switches. [ABSTRACT FROM AUTHOR]

Boolean and logical hypercubes are discussed as providers of tags to logical object sets, transforming them into logical tagged sets, a generalization of fuzzy sets. The equivalence of Boolean and logical sets permits to consider natural tags as an equivalent basis of logical tagged sets. Boolean hypercube concatenation easily allows studying how Boolean information is transmitted. From there a Gödel-like behavior of Boolean hypercubes and thus of logical object sets can be unveiled. Later, it is discussed the iterative building of natural numbers, considering Mersenne numbers as upper bounds of this kind of recursive construction. From there information acquisition, recursive logic, and artificial intelligence are also examined.

Multivalued flip-flops play an important role in multivalued circuits, and their clocks can also be multivalued. According to the switching rule of multivalued clocks and the operating principle of latches, this study proposes an effective method of handling multivalued clocks and a novel odd-even multiplexer for all-edges-triggered flip-flop (AETFF) based on multivalued clocks. The AETFFs structure consisting of odd-even multiplexers i.e. the oeAETFF structure not only senses every edge of multivalued clocks and functions properly, but also is much simpler and more efficient than the previous one. According to the oeAETFF structure, binary or multivalued AETFFs based on arbitrary radices clocks can be easily obtained with a simpler circuit. The oeAETFF structure not only can be implemented by CMOS technology, but also could be used as a helpful reference to guide the flip-flops design with the next-generation devices suitable for multivalued logic. At last, a CMOS quaternary oeAETFF based on quaternary clock is implemented as an instance of the oeAETFF structure. It is validated to function properly with a simpler circuit and higher efficiency by simulation and comparison. [ABSTRACT FROM AUTHOR]

This article deals with an alternative interpretation of syllogistics, different from the classical (extensional) one: an intensional one, in which subject and predicate are not associated with a set of individuals (the extension of the concept) but a set of attributes (the content of the concept). The authors of the paper draw attention to the fact that this approach was first proposed by Leibniz in works on logical calculus, which for a long time remained in the shadow of his other philosophical works. Currently, the intensional approach is gaining more and more popularity due to the development of non-classical logics, and the article will present several existing intensional formal syllogistic semantics. The paper will also consider another historical approach to syllogistics, associated with the name of the Russian logician Nikolai Vasiliev, who is not only one of the founders of non-classical (non-Aristotelian logic) but also of a different intensional interpretation of such logic. The authors, along with the already known formalizations of Vasiliev's ideas, present two new systems. One of them is a reconstruction of one type of imaginary logic with statements of three qualities: affirmative and two types of negative statements (with absolute and ordinary negation). The second system is the one that is adequate to semantics, in which instead of the four classical ones, only three types of statements are presented (two particular statements are replaced by one -- accidental), and their significance is determined through the relation of the classical logical entailment. Both of them are interpreted intensionally. The intensional approach in logic and, in particular, in syllogistics allows us to expand the class of accepted principles (which occurs due to the expansion of the class of correct moods of syllogisms). [ABSTRACT FROM AUTHOR]

Generalized Rademacher functions, constructed as a sequence of elements of Galois fields are intended to find the spectral representation of signals with levels. These functions form a complete basis on the interval corresponding to -1 discrete time intervals and for passing into the classical Rademacher functions. The advantage of such spectra obtained using Galois Fields Fourier Transform is that the range of variation of the spectrum amplitudes remains the same as the range of variation of the original signal, which is modeled on discrete time functions taking values in the Galois field. [ABSTRACT FROM AUTHOR]

In this paper, we suggest an implementation of non-commutative logic and apply its operators for decision-making in a group of autonomous agents. The suggested operators extend the uninorm and absorbing norm aggregators and use an additional asymmetry parameter that defines the “level of non-commutativity”. The value of this parameter is specified using the perception bias of humans measured in the experiments. The suggested operators and decision-making method are illustrated by the simulated behavior of mobile robots in the group, which verified the possibility of processing systematic sensing errors, as well as of distinguishing and mimicking the biased decisions.

Negative differential transconductance (NDT) devices have emerged as promising candidates for multivalued logic computing, and particularly for ternary logic systems. To enable computation of any ternary operation, it is essential to have a functionally complete set of ternary logic gates, which remains unrealized with current NDT technologies, posing a critical limitation for higher-level circuit design. Additionally, NDT devices typically rely on heterojunctions, complicating fabrication and impacting reliability due to the introduction of additional materials and interfaces. Here, we utilize an electron beam to develop tungsten diselenide (WSe 2 ) homojunction NDT devices with W-shaped current-voltage ( I - V ) characteristics. We demonstrate that electron beam enables the manipulation of Se atoms in WSe 2 , facilitating controllable and spatially precise tailoring of the WSe 2 work function. The electron-beam treatment applied to a part of the WSe 2 channel induces a lateral homojunction and ultimately results in the W-shaped I - V curves, which enable both one-input and two-input ternary logic gates. We propose and implement a balanced circuit design for two-input ternary NAND, AND, NOR, and OR gates, featuring a low device count, full-swing operation, and minimized output signal variations. Together with three types of ternary inverters also designed in this work, they form a functionally complete set of ternary logic gates─a prerequisite for practical ternary computing. This work addresses a critical gap in the development of NDT-based ternary computing by ensuring functional completeness and highlights the versatility of electron-beam treatment as an engineering tool for tailoring the properties of two-dimensional van der Waals materials.

Ternary logic device technologies have been actively researched due to the potential benefits such as lower power consumption, smaller device count, smaller area, and higher data processing density, compared to their binary counterparts. In this work, scaling prospect of ZnO stacked nanosheet channel ternary field effect transistor has been investigated. The benefits of scaling geometric parameters such as gate dielectric thickness, channel length, and source/drain charge injection area are examined. 90 % lower power consumption in the intermediate state is achieved at Vdd = 1 V with a noise margin of 130 mV, compared to other emerging ternary logic devices. The feasibility for stable ternary circuit operation is confirmed as well. [ABSTRACT FROM AUTHOR]

It is shown that the creation of artificial intelligence systems, gradually approaching human intelligence, cannot be limited by binary logic and the classical interpretation of the category of truth. The nature of human thinking is variable, which requires the use of flexible algorithmic platforms that operate with multivalued logic. It is shown that the existing approaches to the interpretation of the essence of intelligence, going back to the Turing test, are not consistent. More adequate is a criterion built on the ability of the intellect to lie, including creative particulars. It is shown that using multi-valued logic is a promising tool for constructing the algorithmic basis of artificial intelligence. It is shown that the use of just such logic is of interest from the point of view of studying self-organization processes in a telecommunication environment, resulting in the appearance of "spontaneous intelligence", too. An analogue of such intelligence, for example, is the phenomenon of bureaucracy. It is shown that the question of the essence of the intellect is a prerequisite for the further development of non-trivial logical systems since the functioning of the intellect cannot be reduced to the operations of classical formal logic. [ABSTRACT FROM AUTHOR]

We discuss the problems of transition to the logic synthesis of multivalued digital structures for computer technology and automatic control problems, including the processing of signals from current-output sensors. An algebraic structure for the synthesis of multivalued current circuits based on linear algebra is proposed. The functional capabilities of linear and Boolean algebras for the development and application of bases for the logic synthesis of multivalued digital structures are considered. Simulation-based estimates of the values of technical parameters of multivalued current circuits are given. [ABSTRACT FROM AUTHOR]

This paper proposes a read disturb-free, ternary SRAM cell utilizing 17 Carbon Nanotube Field-Effect Transistors (CNFET). The proposed ternary SRAM cell works on two voltage levels and stores three high, low, and middle voltage levels. The proposed SRAM is energy efficient as the Power Delay Product (PDP) is less during the write and read operations to the past proposed designs. The proposed memory cell underwent temperature and process variations. The proposed ternary memory cell is least affected by temperature and process variations. The proposed ternary SRAM cell proved robust against the diameter of carbon nanotube ($D_{CNT}$), and the channel length of the CNFET ($L_{ch}$) variation in the Monte-Carlo analysis. According to the existing layout design rules of CNFET, the proposed SRAM cell acquires minimum area compared to previously proposed designs. [ABSTRACT FROM AUTHOR]

A multivalued logic (MVL) device can achieve greater data density with a smaller footprint than a traditional binary logic device. In this study, a ternary logic inverter based on negative capacitance FETs (NCFETs) without additional footprints has been realized. By enhancing the amplification in surface potential owing to the utilization of the negative capacitance, the third intermediate state can be successfully obtained at VDD/2 in the conventional binary CMOS inverter. The third intermediate state arises due to no-saturation effect of drain current, and the noise margin of the third intermediate state (NMM) can be optimized by changing ferroelectric thickness or annealing temperature of ferroelectric material. The influence of remnant polarization (Pr) and coercive electric (EC) variation on the ternary logic inverter was investigated based on experimental data. Moreover, a ternary logic 8T SRAM with transmission gate logic (TGL) was proposed, and the results show that the proposed 8T SRAM cell exhibits nondestructive read and reliable write operations for all three states. [ABSTRACT FROM AUTHOR]

Abstract The recent advancements in multivalued logic gates represent a rapid paradigm shift in semiconductor technology toward a new era of hyper Moore's law. Particularly, the significant evolution of materials is guiding multivalued logic systems toward a breakthrough gradually, whereby they are transcending the limits of conventional binary logic systems in terms of all the essential figures of merit, i.e., power dissipation, operating speed, circuit complexity, and, of course, the level of the integration. In this review, recent advances in the field of multivalued logic gates based on emerging materials to provide a comprehensive guideline for possible future research directions are reviewed. First, an overview of the design criteria and figures of merit for multivalued logic gates is presented, and then advancements in various emerging nanostructured materials—ranging from 0D quantum dots to multidimensional heterostructures—are summarized and these materials in terms of device design criteria are assessed. The current technological challenges and prospects of multivalued logic devices are also addressed and major research trends are elucidated.

Ternary logic has been studied for several decades as it can offer significant advantages to reduce the number of interconnects and the complexity of operations. However, the excessive transistor count of the existing ternary logic gates can diminish these advantages in practice. In this brief, based on the negative capacitance (NC) feature of the ferroelectric materials and the well-proven electronic properties of the carbon nanotube field-effect transistor (CNTFET), we have proposed ultra-compact ternary logic gates. After developing a NC-CNTFET model, we have designed a 2-transistor ternary inverter, a 4-transistor ternary NAND, and a 4-transistor ternary NOR with the structures and transistor counts similar to the binary complementary metal-oxide-semiconductor (CMOS) logic. The simulation results ascertain the correct and robust functionality of the proposed ternary gates, even in the presence of process variations. Our proposed ternary inverter, NAND, and NOR gates lead to on average 65%, 60%, and 60% improvements in transistor count, 79%, 83%, and 77% improvements in the area, and 34%, 61%, and 54% improvements in energy-delay product (EDP) as compared to the previous state-of-the-art ternary gates. Our approach accentuates that the proposed ternary gates are the potential candidates for demonstrating more complex multi-valued arithmetic-logic units. [ABSTRACT FROM AUTHOR]

The aim of this paper is to design low-threshold variation, four-state/two-bit Si/SiGe quantum-well n- and p-channel spatial wavefunction-switched field-effect transistors (SWS-FETs). This is achieved by incorporating high-k lattice-matched ZnS–ZnMgS gate dielectric layers resulting in low interface charge. Quantum simulations show switching of electron wavefunction from the lower to the upper Si quantum well in the n-channel as the gate voltage is increased. In the p-channel case, the hole wavefunction switches from the upper to the lower SiGe quantum well. The novelty is in the use of high-mobility metal-oxide-semiconductor (MOS)-gate modulation-doped (MOD) SWS-FETs. The low-threshold lattice-matched gate insulator SWS-FETs are scalable to sub-7 nm and are compatible with quantum-dot nonvolatile random-access memories (QD-NVRAMs). In terms of multivalued logic (MVL) gates, our circuit simulations using the Berkeley Short-channel IGFET Model (BSIM)-based analog behavioral model (ABM) have shown two-bit/four-state output–input transfer characteristics in SWS-complementary metal oxide semiconductor (CMOS) inverters having two Si/SiGe quantum-well channels. In addition, two-bit static random-access memories (SRAMs) are designed, resulting in significantly reduced FET count and power dissipation. Finally, integration of multivalued SWS-CMOS logic, multibit QD-NVRAM cells, and SWS-based SRAMs and registers is presented. [ABSTRACT FROM AUTHOR]

The recent advancements in multivalued logic gates represent a rapid paradigm shift in semiconductor technology toward a new era of hyper Moore's law. Particularly, the significant evolution of materials is guiding multivalued logic systems toward a breakthrough gradually, whereby they are transcending the limits of conventional binary logic systems in terms of all the essential figures of merit, i.e., power dissipation, operating speed, circuit complexity, and, of course, the level of the integration. In this review, recent advances in the field of multivalued logic gates based on emerging materials to provide a comprehensive guideline for possible future research directions are reviewed. First, an overview of the design criteria and figures of merit for multivalued logic gates is presented, and then advancements in various emerging nanostructured materials—ranging from 0D quantum dots to multidimensional heterostructures—are summarized and these materials in terms of device design criteria are assessed. The current technological challenges and prospects of multivalued logic devices are also addressed and major research trends are elucidated. [ABSTRACT FROM AUTHOR]

Some structural properties are discussed of the functions in . We describe the properties of functions not belonging to the maximal subalgebras , , and and show that the maximal cardinality of the basis in is equal to 8. [ABSTRACT FROM AUTHOR]

This article proposes a novel structure for tunneling-based ternary-complementary metal-oxide-semi conductor (T-CMOS) to break through the power scaling constraints of conventional binary-CMOS. The previous T-CMOS uses off-leakage band-to-band tunneling (BTBT) currents generated at the deep drain-to-substrate junction for the third voltage state, which allows ternary inverter configuration with only two single transistors. However, the high-dose ion implantation for the BTBT layer must affect the channel doping concentration, leading to the threshold voltage fluctuation. To avoid the interference of the BTBT layer dopants to the channel as well as to maximize the electrostatic gate controllability, vertically stacked gate-all-around (GAA) field-effect transistor (GAAFET)-type T-CMOS device is proposed. By simply changing the ground plane (GP) doping concentration in existing GAAFET fabrication, the BTBT layer can be formed completely apart from the suspended channel layers. The changes of the transfer characteristics and the transient output voltage characteristics depending on the key parameters such as the GP doping concentration and the gate work function are thoroughly analyzed for the proposed GAA T-CMOS through mixed-mode TCAD device and circuit simulations. It is concluded that the two key parameters should be optimized, otherwise the margin for the third voltage state and the switching speed is seriously degraded. [ABSTRACT FROM AUTHOR]

Kulicki and Trypuz (2016) introduced three systems of multivalued deontic action logic to handle normative conflicts. The first system suggests a pessimistic view on normative conflicts, according to which any conflicting option represents something forbidden; the second system suggests an optimistic view, according to which any conflicting option represents something obligatory; finally, the third system suggests a neutral view, according to which any conflicting option represents something that is neither obligatory nor forbidden. The aim of the present paper is to propose a fourth system in this family, which comes with a realistic view on normative conflicts: a normative conflict remains unsolved unless it is generated by two or more normative sources that can be compared. In accordance with this, we will provide a more refined formal framework for the family of systems at issue, which allows for explicit reference to sources of norms. Conflict resolution is thus a consequence of a codified hierarchy of normative sources. [ABSTRACT FROM AUTHOR]

Multivalued logic (MVL) is an effective way to increase device integration in semiconductor circuits. The major problem for MVL implementation is the availability of proper semiconductor devices. Different quantum structures and their application in different semiconductor devices help them implement the MVL circuit. In this work, the designed graphic user interface will provide more flexibility to the user to highlight the application of different semiconductor devices for MVL implementation. Users can experience the variation of device's characteristics and their feasibility in the application of MVL effectively with this software package. [ABSTRACT FROM AUTHOR]

The performance of a silicon nanotube-based feedback field-effect transistor (SiNT FBFET) with a core-source architecture has been explored in this work for the use in logic-in-memory (LIM) applications. Both n-channel and p-channel FETs with extremely symmetric transfer characteristics and a high O N / O F F current ratio of 10 9 are implemented in a single structure using the core and outer gates. SiNT FBFET exhibits significant data retention attributes during memory operations for up to 10 3 s. The SiNT FBFET-based inverter circuit retains output logic states of "1" and "0" for 1.705 s and 1.948 s, respectively, at megahertz operating frequency without standby power consumption. Additionally, SiNT FBFET has also been used to build ternary NAND/NOR logic gates with memory functionality. Numerical mixed-mode simulations of the circuits have been carried out using the commercially available Synopsys "Sentaurus" TCAD tool for examining the performance and memory characteristics of SiNT FBFETs. This study demonstrates the possible use of SiNT FBFET in multivalued logic systems and the development of next-generation memory devices. • A reconfigurable silicon nanotube-based FBFET with a high O N / O F F current ratio of 10 9 and symmetrical current–voltage characteristics for both n and p-channel modes of operation is demonstrated. • A high retention time of 10 3 s in O N / O F F states for both n- and p-channel modes of operation has been observed. • The device achieves superior retention times for output logic states (1.705 s for '1' and 1.948 s for '0') without standby power consumption, aiding in designing logic-in-memory (LIM) features for an inverter. • Universal ternary NAND (TNAND) and ternary NOR (TNOR) logic gates with memory operations have been successfully implemented using SiNT FBFETs. [ABSTRACT FROM AUTHOR]

We discuss, using recent results on the thermodynamics of multivalued logic, the difficulties and pitfalls of how to apply the Landauer’s principle to thermodynamic computer memory models. The presentation is based on Szilard’s version of Maxwell’s demon experiment and use of equilibrium Thermodynamics. Different versions of thermodynamic/mechanical memory are presented – a one-hot encoding version and an implementation based on a reversed Szilard’s experiment. The relationship of the Landauer’s principle to the Galois connection is explained in detail.

In this paper, a novel algorithm called bi-objective elite differential evolution (BOEDE) is proposed to optimize multivalued logic (MVL) networks. It is a multiobjective algorithm completely different from all previous single-objective optimization ones. The two objective functions, error and optimality, are put into evaluating the fitness of individuals in evolution simultaneously. BOEDE innovatively uses an archive population with different ranks to store elite individuals and offsprings. Moreover, a characteristic updating method based on this archive structure is designed to produce the parent population. Because of the particularity of MVL network problems, the performance of BOEDE to solve them is further improved by strictly distinguishing elite solutions and Pareto optimal solutions, and by modifying the method of dealing with illegal variables. The simulations show that BOEDE can collect a great number of solutions to provide decision support for a variety of applications. The comparison results also indicate that BOEDE is significantly better than the existing algorithms. [ABSTRACT FROM AUTHOR]

Memristors with small size, fast speed, low power, CMOS compatibility and nonvolatile modulation of device resistance are promising candidates for the next-generation data storage and in-memory logic computing paradigm. In comparison to the binary logics enabled by memristor devices, multi-valued logics can provide higher computation efficiency with simple operation scheme, reduced circuit complexity, and smaller chip area. In this contribution, we demonstrate that all the 27 univariate ternary logic operations can be realized with a single ZnO three-state resistive switching memristor in at most three steps. The nonvolatile modulation characteristics of the memristor allow the read step to be independent of the logic operation and capacitate logic-in-memory applications. The present methodology could be beneficial for constructing future high-performance computation architectures. [ABSTRACT FROM AUTHOR]