Logic‐in‐Memory Operation of Ternary NAND/NOR Universal Logic Gates using Double‐Gated Feedback Field‐Effect Transistors

Abstract In this study, the logic‐in‐memory operations are demonstrated of ternary NAND and NOR logic gates consisting of double‐gated feedback field‐effect transistors. The component transistors reconfigure their operation modes into n‐ or p‐channel modes by adjusting the gate biases. The highly symmetrical operation between these operation modes with an excellent on‐current ratio of 1.03 enables three distinguishable and stable logic levels in the ternary logic gates. Moreover, the ternary logic gates maintain the three logic states for several tens to hundreds of seconds under zero‐bias condition. This study demonstrates that the ternary logic gates are promising candidates for next‐generation low‐power computing systems.