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In the present work, we investigate the impact of structure dimensional parameters on the short channel effects which occurs especially below 20 nm regime particularly gate induced drain leakage (GIDL) current. Using technology computer aided design simulation (TCAD), we have examined the GIDL for SiGe as source/drain in NTJLFET. The structural dimensional parameters such as the nanotube thickness, core and outer gates thickness and gate electrode work function shows the significant impact on the band to band tunneling in lateral direction (L‐BTBT) which induced GIDL current. It is analyzed that increase in the nanotube thickness and physical oxide thickness increase the GIDL current, while increasing the gate electrode work function, core gate and outer gate thicknesses gives reduced GIDL current. The SiGe S/D NTJLFET produce a remarkable high ION/IOFF ratio ~ 1011. A compact model for GIDL current is also developed which shows the dependency of structure parameters on leakage current. The SiGe has been incorporated as source and drain in NTJLFET which creates the energy band discontinuity. Furthermore, SiGe S/D NTJLFET is fairly compared with the conventional NT JLFET and nanowire (NW) JLFET and shows an improved performance. [ABSTRACT FROM AUTHOR]

In this work, the effects of total dose irradiation on the parasitic bipolar junction transistor (BTJ) in 130 nm PDSOI MOSFETs were investigated. The experimental results demonstrate that irradiation-induced oxide-trap charges can modify the E-B junction barrier, and thereby make the common-emitter gain β 0 of the parasitic BJT in NMOS device increase, while decreasing it in a PMOS device. Additionally, irradiation-generated oxide-trap charges in shallow trench isolation (STI) elevate the surface electrostatic potential of the gate above the STI sidewall, thus providing an additional channel from the emitter to the collector. Moreover, these charges may generate parasitic reverse conductive paths at the STI/Si interface under high dose irradiation, thereby enhancing the leakage current in the front gate channel and diminishing the significance of the parasitic BJT. Under irradiation, the electric field intensity difference between two biases leads to higher β 0 of the parasitic BJT in PG-biased devices than in ON-biased ones. Furthermore, the lifting effect of irradiation on β 0 increases in wide or short channel irradiated devices, which can be explained using simulations and an emitter current crowding effect model. [ABSTRACT FROM AUTHOR]

The origin of a greater decrease in kink drain voltage $V_{kink}$ in floating body PD-SOI MOSFETs with gate lengths shorter than $0.35 ~\mu m$ is newly revealed. The $V_{kink}$ formula as a function of the internal body voltage and $I_{DS}$ is derived by combining the modified impact ionization multiplication factor with the body-source junction I-V equation. The parameters in this formula are extracted from the measured data of $I_{B}$ vs. $V_{BS}$ and ${- I}_{B}/I_{DS}$ vs. $V_{DS}$ in the body contacted devices. By calculating the formula using the extracted parameters, it is newly found that a decrease of the drain-source saturation voltage at a shorter channel is a primary cause for the short-channel effect on $V_{kink}$ reduction.

In this work, the effects of total dose irradiation on the parasitic bipolar junction transistor (BTJ) in 130 nm PDSOI MOSFETs were investigated. The experimental results demonstrate that irradiation-induced oxide-trap charges can modify the E-B junction barrier, and thereby make the common-emitter gain β0 of the parasitic BJT in NMOS device increase, while decreasing it in a PMOS device. Additionally, irradiation-generated oxide-trap charges in shallow trench isolation (STI) elevate the surface electrostatic potential of the gate above the STI sidewall, thus providing an additional channel from the emitter to the collector. Moreover, these charges may generate parasitic reverse conductive paths at the STI/Si interface under high dose irradiation, thereby enhancing the leakage current in the front gate channel and diminishing the significance of the parasitic BJT. Under irradiation, the electric field intensity difference between two biases leads to higher β0 of the parasitic BJT in PG-biased devices than in ON-biased ones. Furthermore, the lifting effect of irradiation on β0 increases in wide or short channel irradiated devices, which can be explained using simulations and an emitter current crowding effect model.

This study describes a single‐gate silicon on insulator junctionless metal–oxide–semiconductor field‐effect transistor (SJL‐MOSFET) with inserted buried 4H‐SiC p‐type layer (B‐SJL‐MOSFET). The embedded p‐type layer is placed at the bottom of the active regions, achieving the full depletion of the channel in the off‐state mode. The p‐type layer affects the depletion region of the channel, which helps us have a full depletion area with a lower gate electrode work function. The main reason for using SiC material instead of silicon is the higher electrostatic integrity and a shorter natural length than silicon, resulting in a better short channel effect (SCE). In addition, the high‐k oxide is stacked for achieving lower natural length and better subthreshold swing (SS). The p‐type layer improves the leakage current (Ioff) by ≈105 in the event that it slightly diminishes the on‐state current (Ion) and improves the SS. Improvement of off‐current is due to higher barriers between source‐channel side and reduces the parasitic BJT in the off‐mode. [ABSTRACT FROM AUTHOR]

The lateral band-to-band tunneling (L-BTBT) leakage mechanism increases the OFF state current and prevents the junctionless transistor from scaling. The effect of L-BTBT on FIN shaped gate Junctionless field effect transistor(JLFET) with the ground plane (GP) in oxide has been investigated. The proposed device is simulated using 3-D Silvaco TCAD and shows that it can mitigate the L-BTBT and leads to efficient volume depletion which relaxes the requirements of ultra-thin silicon thickness and high workfunction of the gate electrode. The results show significantly reduced OFF-state current and high Ion/Ioff ratio even at scaled gate length beyond 10 nm along with the reduction in drain induced barrier lowering and threshold voltage roll-off. Thus, the proposed device shows better performance at sub-10 nm node. [ABSTRACT FROM AUTHOR]

We propose a parasitic BJT-based zero capacitor random access memory (Z-RAM) cell suitable for stand-alone memory applications. In this Z-RAM cell, high-bandgap TiO 2 is used as the source/drain material and silicon as the channel of an n-channel fully depleted silicon-on-insulator MOSFET. Using well-calibrated TCAD simulations, we demonstrate the programming of the proposed Z-RAM cell at low drain voltages, which is a major advantage from an application perspective. At low drain voltage, hole storage is initiated by band-to-band tunnelling, which is subsequently taken over by impact ionization. Large valence band offset between TiO 2 and Si ( Δ E V ≈ 2 eV) is utilized for storing larger number of excess holes inside the body for a longer time. This leads to the improvement of both sense margin and retention time compared to an all-silicon Z-RAM cell. We predict a retention time of 2 s and 70 ms at T = 300 K and 358 K, respectively, for device gate length of 30 nm. We have optimized the device design to obtain a write '0' time of 6 μ s. Multiple non-destructive reading operation for the proposed Z-RAM cell is also demonstrated. [ABSTRACT FROM AUTHOR]

An SOI LDMOS device with improved ruggedness under unclamped inductive switching (UIS) is described based on the substrate-dissipating (SD) mechanism. The key feature of this device is the introduction of a Γ-shape P-island window with a relatively high doping concentration to connect the N-drift region to the P-substrate under the source, which is designed to achieve an avalanche breakdown point at the edge of the P-island instead of near the gate contact. Thus, the avalanche current is shortened to the substrate contact through the P-island and the P-substrate, avoiding the avalanche current to pass through the N± source/P-well junction and thus suppressing the activation of the parasitic bipolar transistor with a relaxed self-heating effect especially in the P-well region. As verified by the Medici device simulation results, the SD mechanism of the device under the UIS condition, may endure a remarkably higher avalanche current as compared with the conventional SOI LDMOS device.

We design and analyze a raised source/drain dopingless junctionless accumulation mode FET (RDJAMFET) on an intrinsic silicon film using charge plasma concept. This device does not have any physical doping or junctions. Using 2-D simulations, we demonstrate that by making use of the physical design parameters, the device can achieve reduced band-to-band tunneling-induced parasitic bipolar transistor action in the off-state as compared with the planar dopingless junctionless FET (DJFET) for sub-20-nm channel length devices. Further, the RDJAMFET has better gate control and shows significant improvements in terms of drain-induced barrier lowering, subthreshold swing, and I\mathrm{\scriptscriptstyle ON} / I\mathrm{\scriptscriptstyle OFF} as compared with the DJFET for sub-20-nm channel length devices. [ABSTRACT FROM AUTHOR]

This paper investigates high-k dielectric field plate (FP) application to optimize the capacitance and avalanche behavior of conventional drain extended NMOS (C_DeNMOS) for enhanced performance and electrothermal safe operating area (SOA) in transient switching applications. Two configurations of high-k dielectric DeNMOS have been investigated: 1) Planar and 2) Trench. Doping of FP is changed from N+ to P+ in Planar, while shallow trench isolation (STI) is placed below the N+ doped FP in the Trench structure to limit surface charge accumulation in comparison to C_DeNMOS. We demonstrate that efficient reduced-surface-field (RESURF) action of high-k dielectric improves the shielding against high lateral fields, enhancing electrical and electrothermal SOA. Furthermore, for electrothermal SOA analysis, unclamped inductive switching (UIS) simulations have been performed, and it is shown that high parasitic BJT trigger voltage (V t1) and second breakdown current (I t2) enable safe turn-off of the device under high current transient conditions. [ABSTRACT FROM AUTHOR]

In this paper a new technique for controlling floating body effect and self-heating effects is proposed. The main idea in the proposed structure is using a L-shape SiGe region in the nano-scale SOI-MOSFET (LS-SOI). The L-shape SiGe region is located in the source region and is extended under channel. The difference band gap between silicon and silicon–germanium cause discontinuity in band diagram which helps to collect channel holes. Reducing the hole density in channel of the proposed LS-SOI in comparison to conventional SOI-MOSFET (C-SOI) results in suppressed floating body effect. Also, the SiGe region under the channel decreases the lattice temperature in the LS-SOI. Replacing the SiGe with higher thermal capability than buried oxide is useful to have a reliable structure. Moreover, effective mobility, off current and sub-threshold swing improves in the proposed structure. [ABSTRACT FROM AUTHOR]

The Super-Junction power Metal-Oxide-Semiconductor Field-Effect-Transistor (SJ-MOSFET) is one of the main switches in solar, lighting, consumer, server, and telecom applications. Among other market requirements a long lifetime is crucial, thus device robustness and reliability are decisive in quality assessment. Several failures are attributed to the action of the parasitic Bipolar Junction Transistor (BJT) inherent to the physical structure of the SJ-MOSFET. Our purpose is to gain insight into the role of the parasitic BJT under fast voltage pulse condition and to determine if the Transmission Line Pulse (TLP) can be used as a new method for predicting the Single Event Burnout (SEB) sensitivity of SJ-MOSFETs. SEB is caused by extreme localized triggering of the parasitic BJT while the whole device is in the off-state. However, TLP is uniform across a device and drives it into the avalanche multiplication regime. We demonstrate by direct comparison to equivalent SJ-Diodes that the parasitic BJT stabilizes the SJ-MOSFET when subjected to high voltage pulses generated by a TLP system. We conclude that the fast voltage method is not suited for emulating cosmic ray induced failure, but shows immense potential in analyzing device failure in other regimes. [ABSTRACT FROM AUTHOR]

We present a new parasitic bipolar junction transistor (BJT) enhanced silicon on insulator (SOI) laterally double diffused metal oxide semiconductor (LDMOS), called BJT enhanced LDMOS (BE-LDMOS). The proposed device utilizes the parasitic BJT present in an LDMOS to increase the drain current for a given gate voltage, resulting in a reduction in the ON-resistance by 26.2 % and improving the switching speed by 7.8 % for BE-LDMOS as compared to the comparable LDMOS. These improvements are without degradation in other performance parameters such as off state breakdown voltage and transconductance. The process steps for fabricating BE-LDMOS are same as that for LDMOS except for an additional metal contact. [ABSTRACT FROM AUTHOR]

This paper proposes a novel structure of Double Gate (DG) MOSFET to control the impacts of floating body effect. Floating body effect increases hole concentration in the channel region due to the impact ionization. In this novel structure which is named as SiGe Region in DG-MOSFET (SR-DG) two spacers are considered in both sides of gate region and a SiGe zone is incorporated in gate–source spacer. The SiGe region with lower band gap than silicon collects the excess hole in the channel. Our simulation with two dimensional ATLAS simulator shows that the proposed SR-DG improves the performance of DG-MOSFET in terms of threshold voltage, breakdown voltage and electric field. Also, the impacts of parasitic bipolar junction transistor (BJT) are controlled significantly. [ABSTRACT FROM AUTHOR]

In this paper, a novel bipolar junction transistor (BJT) structure is proposed for high matching characteristics and its performance is compared with a conventional BJT structure. Although the proposed BJT matching structure indicates a decrease of collector current density JC and current gain \beta of about 5.36% and 1.02% compared with those of the conventional BJT structure, the matching characteristics of the collector current (AIC) and the current gain (A\beta) for the proposed structure are improved by about 31% and 24%. The improved matching characteristic of the proposed structure is believed to be due to the reduced effect of the deep n-well or the reduced current path from emitter to collector. [ABSTRACT FROM AUTHOR]

Heavy-ion broadbeam results from a 90 nm process are presented for five inverter chains with varying n-well contact schemes. Results show that inverters with the smallest percentage of n-well contact area within an n-well produced the longest and most frequent single-event transients (SETs). As the percentage of n-well area contacted increases above 2%, the pulse width and number of SETs levels-off. A result indicating an optimized percentage of n-well area contacted can be calculated that minimizes the pulse width and number of SETs in a digital circuit. [ABSTRACT FROM PUBLISHER]

We propose a BJT-based floating-body 1T-DRAM cell made of a novel heterostructure suitable to low-power DRAM technology. Based on the numerical simulation, we verify that the proposed structure is capable of reducing the breakdown voltage and single-transistor latch bias in the BJT-based 1T-DRAM, which largely depends on the impact ionization and parasitic BJT through enhancement of the current gain (\beta). Moreover, it is discerned that the novel structure with the SiGe structure has advantages of dynamic refresh characteristics due to reduced bit-line disturb compared with the normal Si device. [ABSTRACT FROM PUBLISHER]

This letter investigates fin-width dependence on single-transistor latch (STL) for bipolar-junction-transistor (BJT)-based 1T-DRAM through experiments. The minimum drain voltage (Vlatch) for the activation of a parasitic lateral BJT in SOI FinFET was measured at various gate lengths (LG's) and fin widths (Wfin's). The multiplication factor and current gain of the parasitic BJT in SOI MOSFET are introduced as determinant factors. The experimental results clearly show that the value of Vlatch is reduced in a shorter LG and wider Wfin device. It was found that the nonlocal effect retards the reduction of Vlatch as FinFET scales down. [ABSTRACT FROM AUTHOR]

• The compact modeling of the transient leakage current caused by parasitic BJT in gate-all-around MOSFET. • The physics based model is considering accumulation conditions, which is indispensable to GAA MOSFET with low-doped body. • The model accurately predicts the current when varying the device structure and bias condition. In this study, transient leakage current caused by a parasitic bipolar junction transistor (BJT) in nanowire-type gate-all-around metal–oxide–semiconductor field-effect transistors is physically modeled for circuit design. The model considers the majority carrier concentration in the body, which is modulated by the gate-to-body bias. The parasitic BJT gain is dependent on the majority carrier concentration, which exceeds the body doping concentration in transient conditions. Three-dimensional technology computer-aided design simulation is performed to verify the model. The model accurately predicts the transient leakage current according to various structural parameters. [ABSTRACT FROM AUTHOR]