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High-bandwidth density and energy-efficient readout interfaces connecting the superconductor electronic (SCE) integrated circuits (IC) with room-temperature environments are essential for emerging quantum and classical superconducting computing applications, which motivate the design of cryogenic optical links. This work addresses four challenges in this communication link. First, a comprehensive link model, which consists of superconductor and semiconductor electronic/photonic components, is built to analyze the performance and energy efficiency of the link. Then, a novel cryogenic optical link based on the monolithic silicon photonic process and laser-forwarded coherent architecture is proposed to balance power consumption at cryogenic and room-temperature environments and improve overall energy efficiency. Next, an accurate device model is necessary for circuit design nowadays, while little is known about the transistor's behavior at cryogenic temperatures. A detailed theoretic analysis and device characterization of transistors from monolithic silicon photonic processes is presented. Following that, a proof-of-concept single-chip CMOS electronic-photonic cryogenic transmitter is designed and implemented in the 45RFSOI process. The link experiment at cryogenic temperatures with the direct drive from superconductor IC demonstrates its function, performance, and energy efficiency. Compared to the existing solution, our work shows the best energy efficiency by eliminating the extra discrete cryogenic amplifier requirement. Finally, a new type of EOPLL, including a boundless phase shifter-based phase rotator and dLev comparator-based phase estimator, is proposed to solve the inevitable time-varying phase offset issue in the laser-forwarded coherent architecture. A proof-of-concept coherent receiver with proposed EOPLL is designed and implemented in the 45SPCLO process.

Data center traffic continues to experience considerable growth due to the vast amount of data generated by cloud computing, augmented reality, and the internet of things and Intra-data center traffic makes up to 77% of the total traffic, so improvements in spectral efficiency, bandwidth and power consumption of data center interconnections contribute to overall energy efficiency. Intra-data center traffic interconnects aim for data rates above 200 Gbps per wavelength while reducing power consumption. Coherent links leveraging orthogonal polarization and quadrature modulation schemes are an energy-efficient alternative approach to commonly used intensity modulation direct detection (IMDD). A component to this vision is the realization of low-power, broadband optical receivers for quadrature phase shift keying (QPSK) or higher-order coherent waveforms.Improvements in energy efficiency through increased data rate and reduction in power consumption is also significantly affected by electronic-photonic integration. Co-packaged optics have been proposed as one approach to fulfill this demand by minimizing the high-speed I/O power consumption. Nevertheless, parasitic resistance, inductance and capacitance between electronic and photonic circuits deteriorates the high-speed performance and requires power hungry equalization, thereby eliminating improvements in energy efficiency. Consequently, packaging approaches that enable either monolithic or 3D integration of heterogeneous ICs, i.e. silicon photonic and electronic ICs, are promising approaches to improve performance.The focus of this work is to develop energy-efficient optical fiber communication links through studying the system architecture trade-offs, as well as integrated opto-electrical circuit design for the link implementation. Performance degradation due to packaging effects is also studied and quantized. Several fiber optic communication links have been designed and measured. The first monolithically integrated CMOS-Photonic coherent optical receiver was implemented and achieved 80 Gbps with 1.2 pJ/bit energy efficiency. The O-band receiver was redesigned to further improve the performance and achieved above 100 Gbps and a record energy efficiency below 1 pJ/bit. These results show the possibility to implement O-band coherent optical links to support 200 Gbps per wavelength below 10 pJ/bit for next generation intra data center applications.

Optical telecommunications currently cover a significant part in the digital data exchanges. The increasing rate of the exchanged data is pushing to the continuous improvement of involved technologies. Silicon photonics is a part of this development and aims to closely co-integrate optical and electronic components, using optoelectronics components as interfaces. This thesis is part of this theme and more particularly in the context of the characterization PIC25G technology developed by STMicroelectronics. It aims to bring optical connections directly to the servers of internet data centers in order to increase the overall data exchange performances.Like all technologies, it is necessary to perform a continuous monitoring of its performances through electrical and, here, optical characterization. But it is also important to be able to assess as accurately as possible the lifetime of these components under nominal conditions. A reliability study of silicon photonics components was therefore essential for STMicroelectronics. However, very few studies have been done on this topic. The objective of this thesis is to present the study of the reliability of the optoelectronic components used in telecommunications applications.This manuscript is organized into three main parts. The first will present in detail the context of this study, its challenges, and the objectives we set. A second part will be dedicated to the installation of an optoelectronic characterization bench and its validation, then will present the first tests performed on packaged components. The third chapter will present the different characterizations performed on photodetectors of PIC25G technology, we will show how the degradation of the performances observed during stress tests can be explained by a physical model that we will detail and validate. Finally, the perspectives opened by this work will be addressed in the more general context of the reliability of optoelectronic devices and integrated photonics., Les télécommunications par voie optique recouvrent de nos jours une part majoritaire dans l’échange des données numériques. L’augmentation des débits et des volumes de données échangées poussent à l’amélioration constantes des technologies qui les sous-tendent. La photonique sur silicium s’inscrit dans ce développement et vise à co-intégrer aux plus près les composants optiques et les composants électroniques en utilisant comme interface les composants optoélectroniques. Cette thèse s’inscrit dans cette thématique et plus particulièrement dans le cadre de la caractérisation de la technologie PIC25G développée par STMicroelectronics. Cette dernière a pour objectif de pouvoir amener les connexions optiques directement sur les serveurs des centres de données internet, pour ainsi augmenter les performances globales de l’échange des données.Comme toutes technologies, il est nécessaire de mener un suivi continu de ses performances par de la caractérisation électrique et, ici, optique. Mais il est aussi crucial de pouvoir évaluer le plus précisément possible la durée de fonctionnement de ces composants dans des conditions nominales. Une étude de fiabilité des composants de la photonique sur silicium était donc indispensable pour STMicroelectronics. Cependant, très peu d’études ont été menées sur ce sujet. L’objectif de cette étude est de présenter l’étude de la fiabilité des composants optoélectroniques visant les applications de télécommunication.Ce manuscrit est organisé en trois parties principales. La première d’entre elles présentera de façon détaillée le contexte de cette étude, ses enjeux ainsi que les objectifs que nous nous fixons. Une deuxième partie sera consacrée à la mise en place d’un banc de caractérisation optoélectronique, à sa validation, puis présentera les premiers tests réalisés sur des composants mis en boitier. Le troisième chapitre regroupera quant à lui les différentes caractérisations effectuées sur des photodétecteurs de la technologie PIC25G, nous y montrerons comment les dégradations de performance observées lors de tests de stress réalisés peuvent être expliquées par un modèle physique que nous détaillerons et validerons. Finalement, les perspectives ouvertes par ces travaux seront abordées non seulement par rapport à la problématique de STMicroelectronics mais aussi dans le cadre plus général de la fiabilité des dispositifs optoélectroniques et photoniques intégrés.

We propose and experimentally demonstrate a silicon photonic circuit that can perform the comparison operation of two-bit digital signals based on microring resonators (MRRs). Two binary electrical signals regarded as two operands of desired comparison digital signals are applied to three MRRs to modulate their resonances through the microheaters fabricated on the top of MRRs, respectively (here, one binary electrical signal is applied to two MRRs by a 1×2 electrical power splitter, which means that the two MRRs are modulated by the same binary electrical signal). The comparison results of two binary electrical signals can be obtained at two output ports in the form of light. The proposed device is fabricated on a silicon-on-insulator substrate using the complementary metal-oxide-semiconductor fabrication process, and the dynamic characterization of the device with the operation speed of 10 kbps is demonstrated successfully.

An integrated electronic-photonic phase-locked loop (PLL) modulates the frequency of a tunable laser for use in frequency-modulated continuous-wave (FMCW) lidar 3D imaging. The proposed lidar can perform 180k range measurements per second. The rms depth precision is 8 $\mu \text{m}$ at distances of ±5 cm from the range baseline. The range window is 1.4 m, with a precision of 4.2 mm at the edges of the window. Optical circuitry, including input light couplers, waveguides, and photodiodes, is realized on a 3 mm $\times $ 3 mm silicon-photonic chip. The 0.18- $\mu \text{m}$ CMOS ASIC of the same area comprises the front-end transimpedance amplifier, analog electro-optical PLL, and digital control circuitry consuming 1.7 mA from a 1.8 V supply and 14.1 mA from a 5-V supply. The latter includes 12.5-mA bias current for the distributed Bragg reflector section of the tunable laser. The two chips are integrated using through-silicon-vias implemented in the silicon-photonic chip.

Optical networks-on-chip (NoCs) provide a promising answer to address the increasing requirements of ultra-high bandwidth and extremely low power consumption. Designing a photonic interconnect, however, involves a number of challenges that have no equivalent in the electronic domain, particularly the crosstalk noise, which affects the signal-to-noise ratio (SNR) possibly resulting in an inoperable architecture and hence constraining the network scalability. In this article, we point out the implications of application-driven task mapping on crosstalk effects. We motivate the main rationale of our work and provide a formalization of the problem. Then we propose a class of algorithms that automatically map the application tasks onto a generic mesh-based photonic NoC architecture such that the worst-case crosstalk is minimized. We also present a purpose-built experimental setup used for evaluating several architectural solutions in terms of crosstalk noise and SNR. The setup is used to collect extensive results from several real-world applications and case studies. The collected results show that the crosstalk noise can be significantly reduced by adopting our approach, thereby allowing higher network scalability, and can exhibit encouraging improvements over application-oblivious architectures.

The next generation of Multiprocessor Systems-on-Chip will require communication facilities that cannot be provided by traditional electronic communication infrastructures. Silicon photonics appears today a promising solution to handle future communication needs thanks to ultra-high bandwidth and extremely low-power consumption. However, designing an optical on-chip network requires addressing several challenges that have no equivalent in the electronic domain. In particular, photonic networks-on-chip suffer from considerable power loss, which affects the network scalability and impacts the performance by constraining the total number of wavelengths and hence the available bandwidth. In this paper, we propose an algorithm which automatically maps the IP cores onto a generic mesh-based photonic NoC architecture such that the worst-case power loss is minimized. As the main contribution, we first formulate the problem of power loss aware mapping and then we propose a genetic algorithm to solve it. Experimental results show that the power loss can be significantly reduced enabling much higher scalability of the on-chip photonic interconnect.

We present a design for an on-chip MEMS-actuated Variable Optical Attenuator (VOA) based on Silicon Photonic MEMS technology. The VOA consists of 30 individual mechanically movable MEMS cantilevers, suspended over an integrated, 1 mu m wide bus waveguide, each terminating with two optical attenuation bars. By exploiting the pull-in instability, electrostatic actuation allows to move the individual cantilevers into proximity of the waveguide, leading to scattering of the evanescent field and thus attenuation of the remaining optical power in the waveguide. Electrodes are placed below the cantilevers for electrostatic actuation. Mechanical stoppers are used to avoid contact between the cantilevers and the electrodes and to keep the bars at a precisely defined distance of 60 nm away from the bus waveguide. The attenuator provides nearly zero insertion loss in OFF state, while in ON state, the attenuation range is defined by the number of actuated digital attenuation cantilevers and can be adjusted in discrete increments of only 1.2 dB. Owing to the small size, fast microsecond scale response time can be achieved, and electrostatic MEMS actuation allows for broadband and low-power operation. Our design exhibits a compact footprint of 30 mu m x 45 mu m, attenuation from 0 dB to 36 dB, while keeping return loss below 27 dB. To the best of our knowledge, this is the first presentation of a design of a VOA in Silicon Photonic MEMS technology.

We experimentally investigate the smallest germanium waveguide cavity resonators on silicon that can be designed to work around 1.55 mu m wavelength and observe an almost 30-fold enhancement in the collected spontaneous emission per unit volume when compared to a continuous germanium film of the same thickness. The enhancement is due to an effective combination of (i) excitation enhancement at the pump wavelength, (ii) emission enhancement (Purcell effect) at the emission wavelength, and (iii) effective beaming by the nanoresonators, which act as optical antennas to enhance the radiation efficiency. Our results set a basis for the understanding and engineering of light emission based on subwavelength, CMOS-compatible nanostructures operating at telecommunication wavelengths.

Recently, Silicon Photonics has emerged as a solution for the mass manufacturing of optical transceivers addressing datacenter’s needs in terms of increasing data-rate and reduced cost. Several Silicon-Photonics platforms have been demonstrated using standard Si technology. While these platforms differ in many regards, they all lack a solution for a monolithically integrated light source. To solve this problem, the most commonly proposed approach consists in bonding an InP-stack onto a Si-wafer in order to fabricate a Hybrid III-V/Si laser. However, none of those demonstrations have been made with a standard CMOS-BEOL, preventing a proper electronic-photonic integration. To solve the topographical problem induced by the additional layers, a new integration scheme, called Back-Side, has been developed and is presented in this document.First, the context of this study, a state of the art as well as the presentation of the Back-Side is discussed. The innovation brought by this integration, namely the bonding of the III-V on the back side of the SOI after the structuring of the latter, is then detailed.The correct behavior of a key element to the photonic chip, the grating coupler, is then treated through simulations, fabrication and optical characterizations. We have proved that, under specific conditions, this device has the same measured performances in Back-Side and in Front-Side.The principle of an optical oscillator and then the various modules composing the hybrid laser are then detailed. The implemented laser is based on a hybrid DBR (Distributed Bragg Reflector) III-V/Si cavity. In order to increase the mode confinement in the MQWS (Multi Quantum Wells) and hence ensure a high optical gain, the optical mode is gradually transferred between the III-V waveguide and the silicon waveguide of the hybrid laser by adiabatic tapers, patterned on both sides of the gain zone, to finally be reflected by the mirrors DBR in the silicon.Finally, its manufacturing process is explained before its opto-electronic characterizations are presented. The electrically pumped lasers have been tested under continuous-wave current conditions and the generated light has been collected through the grating coupler to a multi-mode fiber. The fiber coupling losses has been measured to be higher than 10 dB. The output power is up to 1.15 mW at an injection current of 200 mA. The lasing threshold is 45 mA which corresponds to a current density of 1.5 kA/cm2 and the series resistance of the laser contacts is approximately 9 . The threshold voltage is 1.45 V.The laser spectra reflect its single-wavelength laser operation, for different injection currents, with a central wavelength corresponding to the Bragg wavelength of the mirrors. A Side Mode Suppression Ratio (SMSR) of more than 35 dB has been measured. A 4 nm wavelength shift has been observed when injecting 20 mA into both metallic heaters above DBRs.The monolithic integration of a fully CMOS compatible hybrid DBR laser on the backside of a SOI wafer being demonstrated for the first time, implementing CMOS compatible electric interconnects and optical sources on a same chip has could be achieved. This device opens the route to a fully integrated optical transceiver on a Si platform., Ces dernières années, la photonique sur silicium est apparue comme une solution prometteuse pour la fabrication en grande série d'émetteurs-récepteurs optiques répondant aux besoins des centres de données en termes d'augmentation du débit et de coûts réduits. Plusieurs plateformes de photonique sur silicium ont été démontrées en utilisant la technologie Si standard. Bien que ces plateformes diffèrent à bien des égards, elles manquent toutes d'une source de lumière intégrée monolithiquement. Pour résoudre ce problème, l'approche la plus couramment proposée consiste à coller un empilement InP sur une plaque SOI afin de fabriquer un laser hybride III-V/Si. Cependant, aucune des démonstrations n'a été réalisée avec un empilement d’interconnexions métalliques BEOL (Back-End Of Line) standard, empêchant ainsi une intégration électronique-photonique appropriée. Pour résoudre le problème topographique posé par cet ajout de couches, un nouveau schéma d'intégration, appelé intégration Back-Side, a été développé et est présenté dans ce document.Tout d'abord, le contexte de cette étude, un état de l’art ainsi que la présentation du Back-Side est abordé. La nouveauté apportée par cette intégration, à savoir le collage du III-V sur la face arrière du SOI après la structuration de celui-ci, y est alors détaillé.Le bon fonctionnement d’un élément essentiel à la puce photonique, le réseau de couplage, est ensuite abordé à travers des simulations, sa fabrication et des caractérisations optiques. Nous avons prouvé que, sous certaines conditions, ce dispositif possède les mêmes performances mesurées en Back-Side qu’en Front-Side.Le principe de fonctionnement d’une cavité oscillante puis les différents modules composants le laser hybride sont détaillés. Le laser étudié est une cavité hybride DBR (Distributed Bragg Reflector) III-V/Si. Afin d'augmenter le confinement du mode dans le MQWs (Multi Quantum Wells) et donc d'assurer un gain optique élevé, le mode optique est progressivement transféré entre le guide III-V et le guide silicium du laser hybride par des épanouisseurs adiabatiques, structurés dans le SOI de part et d’autre de la zone de gain, pour être enfin réfléchi par les miroirs DBR dans le silicium.Enfin, son processus de fabrication est explicité avant que ses caractérisations opto-électroniques ne soient finalement présentées. Les lasers à pompage électrique ont été testés dans des conditions de courant continu et la lumière générée a été collectée à travers un réseau de couplage par une fibre optique externe multimode. Les pertes de couplage ont été mesurées supérieures à 10 dB. La puissance de sortie est de 1,15 mW à un courant d'injection de 200 mA. Le seuil laser est de 45 mA, ce qui correspond à une densité de courant de 1,5 kA / cm2 et la résistance série des contacts laser est d'environ 9 Ω. La tension de seuil est de 1,45 V. Les spectres lasers reflètent un fonctionnement mono-fréquence, pour différents courants d'injection, avec une longueur d'onde centrale correspondant à la longueur d’onde de Bragg des miroirs. Un SMSR (Side Mode Suppression Ratio) de plus de 35 dB a été mesuré, ce qui prouve la bonne pureté spectrale de ce laser. Un décalage de la longueur d'onde de 4 nm a été observé en injectant un courant de 20 mA dans des chaufferettes métalliques au-dessus des DBRs.L'intégration monolithique d'un laser DBR hybride en face arrière d'une plaque SOI, entièrement compatible CMOS, a été démontrée pour la première fois, la mise en place d'interconnexions électriques compatibles CMOS et de sources optiques sur une même puce a pu être réalisée. Ce dispositif ouvre la voie à un émetteur-récepteur optique entièrement intégré sur une plateforme Si.

Wireless optical networks have been recently proposed to connect Multi Processors directly at chip level. The efficient implementation of these links requires accurate design of antennas and waveguide to antenna couplers. In this work, some plasmonic antennas optimized for on-chip communications will be illustrated and discussed.

High n-type doping in germanium is essential for many electronic and optoelectronic applications especially for high performance Ohmic contacts, lasing and mid-infrared plasmonics. We report on the combination of in situ doping and excimer laser annealing to improve the activation of phosphorous in germanium. An activated n-doping concentration of 8.8 x 10(19) cm(-3) has been achieved starting from an incorporated phosphorous concentration of 1.1 x 10(20) cm(-3). Infrared reflectivity data fitted with a multi-layer Drude model indicate good uniformity over a 350 nm thick layer. Photoluminescence demonstrates clear bandgap narrowing and an increased ratio of direct to indirect bandgap emission confirming the high doping densities achieved.

This paper reports about an efficient method for the numerical simulation of the electrical and optical characteristics, in both steady state and transient conditions, of free carrier injection- or depletion-based electro-optical active devices, based on the low cost technology of hydrogenated amorphous silicon (a-Si:H) and related semiconducting alloys, like a-SiC:H. In particular, our experimental results, recently achieved for low-loss, birefringence-free, single-mode waveguide-integrated phase modulators, are used to tune the many simulation parameters and validate the mixed electro-optic simulation environment. The tool is used to design a Mach–Zehnder Interferometer (MZI)-based modulator enhancing the performances of previous realized devices.

International audience; A silicon integrated wideband common emitter amplifier driver unit in 55 nm SiGe BiCMOS technology designed for a 60 Gb/s silicon photonic segmented Mach-Zehnder Modulator (SE-MZM) is reported in this paper. It achieves a bandwidth of 42.2 GHz (0.3-42.5 GHz), allowing the transmission of an On-Off Keying (OOK) modulated optical signal on a single optical channel with a data rate of up to 60 Gb/s. For a power consumption of 125 mW, it provides a small signal gain of 18 dB and a single-ended peak-to-peak output voltage swing of up to 1.1 V on a 50 Ω output load. The die active area is as small as 204 x 137 µm2.

International audience; Most of the optical networks-on-chip (ONOCs) architectures proposed so far in the literature rely for their operation on wavelength division multiplexing (WDM). A limitation to the WDM approach for on-chip communications stems from the difficulty of integrating light sources on a silicon CMOS compatible platform. Therefore, to optimise the use of the available lasers, a further dimension inherent to optical communications can be leveraged to implement on-chip networking, namely the spatial (modal) one. In mode-division multiplexing (MDM) techniques, distinct communication channels are allocated, on the same common wavelength, to the various modes of a multi-mode waveguide. While for on-chip WDM networks the awareness on the requirements of functional building blocks is well established, for on-chip MDM systems, on the contrary, the design constraints at both device and system levels are still an open issue of investigation. The aim of this contribution is to explore, by means of analytical (scattering matrix formalism) and numerical (FDTD) tools, the design space of different MDM building blocks.

Silicon photonics as a one of the most promising photonic integration technologies has attracted many attentions in recent years. The major feature of this technology is its compatibility with complementary metal-oxide semiconductor (CMOS) processes which makes it possible to integrate optical and electronic devices in a same chip and reduce the cost significantly. Another reason of using silicon photonics is the high index contrast between the silicon core and silicon dioxide cladding which ensures the high density integration of photonic devices on a single chip. Monolithic integration with electronic and optical circuits makes silicon photonics technology suitable for numerous applications. One example is microwave photonics (MWP). MWP is an area that studies the interaction between microwave and optical signal for the generation, processing, control and distribution of microwave signals by means of photonics. Silicon photonics offers a reduction in footprint, losses, packaging cost and power dissipation in MWP systems. This research in this thesis is focused on the design and fabrication of the silicon photonic devices for MWP signal processing and generation. Four MWP systems based on silicon photonic devices are proposed and experimentally demonstrated. 1) A single pass-band frequency-tunable MWP filter based on phase-modulation to intensity-modulation conversion in an optically pumped silicon-on-insulator (SOI) microring resonator (MRR) is designed and experimentally demonstrated. In the proposed filter, a phase-modulated optical signal is filtered by the SOI MRR, to have one first-order sideband suppressed by the MRR notch. The phase-modulated optical signal is converted to an intensity-modulated single-sideband (SSB) signal and detected at a photodetector (PD). The entire operation is equivalent to a single pass-band filter. The frequency tunability is achieved by tuning the resonance wavelength of the MRR, which is realized by optically pumping the MRR. A single pass-band MWP filter with a tunable center frequency from 16 to 23 GHz is experimentally demonstrated. 2) A broadband optically tunable MWP phase shifter with a tunable phase shift using three cascaded SOI MRRs that are optically pumped is designed and experimentally demonstrated. A microwave signal to be phase shifted is applied to an optical single-sideband (OSSB) modulator to generate an optical carrier and an optical sideband. The phase shift is introduced to the optical carrier by placing the optical carrier within the bandwidth of one resonance of the three cascaded MRRs. The experimental results show that by optically pumping the cascaded MRRs, a broadband MWP phase shifter with a bandwidth of 7 GHz with a tunable phase shift covering the entire 360o phase shift range is achieved. 3) A multi tap MWP filter with positive and negative coefficients using a silicon ring resonator modulator (RRM) is proposed and experimentally demonstrated. The RRM is designed and fabricated to operate based on the carrier depletion effect. The positive and negative coefficients are obtained by using opposite slopes of the modulation transmission response of the RRM. Two filter responses with two and three taps are experimentally demonstrated, showing the proof-of-principle for frequencies up to 18 GHz. 4) An approach to generate microwave signal based on enhanced four wave mixing (FWM) in an active silicon waveguide (SiWG) is studied. This SiWG is designed and fabricated, and the use of the active SiWG for MWP frequency multiplication to generate a frequency-sextupled millimeter-wave signal is experimentally demonstrated. Thanks to a reverse-biased p-n junction across the SiWG, the conversion efficiency of the FWM is improved, which leads to the improvement of the microwave frequency multiplication efficiency.

In this paper, we demonstrated a 1 × 4 silicon photonic cascaded arrayed waveguide grating, which is fabricated on a SOI wafer with a 220 nm top Si layer and a 2µm buried oxide layer. The measured on-chip transmission loss of this cascaded arrayed waveguide grating is ~ 5.6 dB, including the fiber-to-waveguide coupling loss. The adjacent crosstalk is 33.2 dB. Compared to the normal single silicon photonic arrayed waveguide grating with a crosstalk of ~ 12.5 dB, the crosstalk of this device has been dramatically increased., {"references":["C. Tsai, H. Taga, C. Yang, Y. Lo, and T. Liang, \"Demonstration of a ROADM using cyclic AWGs,\" Journal of Lightwave Technology 29, pp. 2780-2783, 2011.","C. R. Doerr, L. W. Stulz, D. S. Levy, L. Gomez, M. Cappuzzo, J. Bailey, R. Long, A. Wong-Foy, E. Laskowski, E. Chen, S. Patel, and T. Murphy, Eight-wavelength add-drop filter with true reconfigurability,\" IEEE Photonics Technology Letters 15, pp. 138–140, 2003.","Q. Fang, F. Li, Y. Liu, \"Compact SOI arrayed waveguide grating demultiplexer with broad spectral response,\" Optics Communications 258, pp 155-158, 2006.","X. Tu, T. Liow, J. Song, X. Luo, Q. Fang, M. Yu, and G.Lo, \"50-Gb/s silicon optical modulator with traveling-wave electrodes,\" Optics Express 21, pp 12776-12782, 2013.","J. C. Rosenberg, W. M. J. Green, S. Assefa, D. M. Gill, T. Barwicz, M. Yang, S. M. Shank, and Y. A. Vlasov, \"A 25 Gbps silicon microring modulator based on an interleaved junction,\" Optics Express 20, pp. 26411-26423, 2012.","Q. Fang, L. Jia, J. Song, A. E. J. Lim, X. Tu, X. Luo, M. Yu, and G. Lo, \"Demonstration of a vertical pin Ge-On-Si photo-detector on a wet-etched Si recess,\" Optics Express 21, pp. 23325-23330, 2013.","P. Chaisakul, D. Marris-Morini, J. Frigerio, D. Chrastina, M. Rouifed, S. Cecchi, P. Crozat, G. Isella, L. Vivien, \"Integrated germanium optical interconnects on silicon substrates,\" Nature Photonics 8, pp. 482-488, 2014.","Q. Fang, J. Song, X. Luo, M. Yu, G. Lo, and Y. Liu, \"Mode-size converter with high coupling efficiency and broad bandwidth,\" Optics Express 19, pp. 21588-21594, 2011.","Q. Fang, J. Song, T. Liow, H. Cai, M. Yu, G. Lo, D. Kwong, \"Ultralow power silicon photonics thermo-optic switch with suspended phase arms,\" IEEE Photonics Technology Letters 23, pp. 525-527, 2011.\n[10]\tK. Sasaki, F. Ohno, A. Motegi, T. Baba, \"Arrayed waveguide grating of 70 × 60 μm2 size based on Si photonic wire waveugides,\" Electronics Letters 41, pp. 801-802, 2005.\n[11]\tW. Bogaerts, P. Dumon, D. V. Thourhout, D. Taillaert, P. Jaenen, J. Wouters, S. Beckx, V. Wiaux, R. G. Baets, \"Compact wavelength-selective functions in silicon-on-insulator photonic wires,\" IEEE Journal of Selected Topics in Quantum Electronics 12, pp. 1394-1401, 2006."]}

Asymmetric quantum well systems are excellent candidates to realize semiconductor light emitters at far-infrared wavelengths not covered by other gain media. Group-IV semiconductor heterostructures can be grown on silicon substrates, and their dipole-active intersubband transitions could be used to generate light from devices integrated with silicon electronic circuits. Here, we have realized an optically pumped emitter structure based on a three-level Ge/Si0.18Ge0.82 asymmetric coupled quantum well design. Optical pumping was performed with a tunable free-electron laser emitting at photon energies of 25 and 41 meV, corresponding to the energies of the first two intersubband transitions 0 → 1 and 0 → 2 as measured by Fourier-transform spectroscopy. We have studied with a synchronized terahertz timedomain spectroscopy probe the relaxation dynamics after pumping, and we have interpreted the resulting relaxation times (in the range 60 to 110 ps) in the framework of an out-of-equilibrium model of the intersubband electron−phonon dynamics. The spectral changes in the probe pulse transmitted at pump−probe coincidence were monitored in the range 0.7−2.9 THz for different samples and pump intensity and showed indication of both free carrier absorption increase and bleaching of the 1 → 2 transition. The quantification from data and models of the free carrier losses and of the bleaching efficiency allowed us to predict the conditions for population inversion and to determine a threshold pump power density for lasing around 500 kW/cm2 in our device. The ensemble of our results shows that optical pumping of germanium quantum wells is a promising route toward siliconintegrated far-infrared emitters.

International audience; In this paper, a silicon integrated driver unit, intended for a single-channel NRZ 3D heterogeneous silicon photonic modulator is proposed. It allows data rate of up to 100 Gb/s, which is beyond the current state of the art. It directly controls 160 GHz bandwidth high speed phase modulator (HSPM) segment of a Mach Zehnder Interferometer (MZI). It is fabricated in 55 nm SiGe BiCMOS technology with fT of up to 300 GHz. It features a 300 mW of dc power consumption and delivers a 2.5 Vpp single-ended output swing at 100 Gb/s.

In this book, silicon photonic integrated circuits are combined with electro-optic organic materials for realizing energy-efficient modulators with unprecedented performance. These silicon-organic hybrid Mach-Zehnder modulators feature a compact size, sub-Volt drive voltages, and they support data rates up to 84 Gbit/s. In addition, a wet chemical waveguide fabrication scheme and an efficient fiber-chip coupling scheme are presented.

Future many-core systems will require energy-efficient, high-throughput and low-latency communication architectures. Silicon Photonics appears today as a promising solution to achieve these goals. However, the photonics inability to perform inflight buffering and logic suggests the use of Hybrid Photonic-Electronic architectures. In order to exploit the full potential of photonics, it is essential to thoroughly design the Path-Setup architecture, which is the primary source of performance degradation and power consumption. In this paper, we propose a new power-aware path-setup protocol able to put allocated circuits on a stand-by state, rapidly recovering them when needed. We compare in terms of performance and energy consumption some path-setup architectural solutions that differ from each other in the routing algorithm, the path-setup protocol and the deadlock avoidance technique. The results show that the proposed protocol outperforms other solutions in terms of performance and energy efficiency. In addition, this comparison will help many-core system designers to select the most appropriate path-setup architecture according to traffic characteristics and network size.

High quality factor and small modal volume microcavities allow, thanks to a strong light confinement, an enhancement of light matter interactions and the realization of low energy consumption devices for optical signal processing.In this work, we study the coherent excitation of nonlinear photonic crystal resonators, which is achieved by controlling the pulse time-Frequency relation, enabling nonlinear interaction enhancement.A modeling of the intra-Cavity nonlinear dynamics is conducted using the coupled mode theory, underlying the nonlinear refractive effects contribution in the intra-Cavity pulse energy reduction and distortion.We show that an appropriate pulse time-Frequency relation allow to compensate for the cavity resonance frequency shift, and to maintain the benefit of light localization during the entire excitation.The pulse shaper, made of a pulse-Stretcher combined with a spectral filter, has been specifically designed.Preliminary nonlinear characterizations of silicon nanowires enable to determine the shaped pulses parameters.A very first experimental coherent excitation of an optical resonator is reported, leading to a nonlinear interaction enhancement, and to the control of both the optical bandwidth and nonlinear dynamics of the cavity.; Les microcavités à grand facteur de qualité et faible volume modal permettent, grâce à un fort effet de confinement de la lumière, le renforcement des interactions lumière-Matière et la réalisation de futurs dispositifs pour le traitement optique de l’information à faible énergie de commande. Ce travail de thèse traite du fonctionnement de microcavités à cristal photonique en régime d’excitation cohérente, basé sur des impulsions dont la relation temps-Fréquence est contrôlée afin de renforcer les interactions non linéaires intracavité.La modélisation de la dynamique non linéaire de ces cavités à l'aide de la théorie des modes couplés, a permis de mettre en avant le rôle des non-Linéarités réfractives sur la réduction des effets de localisation au cours de l'excitation.Nous proposons alors de contrôler la dynamique du champ intracavité par un contrôle de la relation temps-Fréquence des impulsions.Cette excitation dite cohérente, repose sur la mise en œuvre d'un montage de mise en forme d'impulsions, constitué d'un étireur d'impulsions et d'un dispositif de filtrage spectral.La caractérisation non linéaire de nanoguides en silicium a permis, en complément du modèle, la détermination précise des paramètres des impulsions.Nous avons ensuite réalisé la toute première démonstration expérimentale de l'excitation cohérente de microcavités, menant à la fois à un renforcement des interactions non linéaires et une réduction des distorsions subies par les impulsions transmises par la cavité.

Dense arrays of micrometric crystals, with areal filling up to 93%, are obtained by depositing GaAs in a mask-less molecular beam epitaxy process onto Si substrates. The substrates are patterned into tall, micron sized pillars. Faceted high aspect ratio GaAs crystals are achieved by tuning the Ga adatom for short surface diffusion lengths. The crystals exhibit bulk-like optical quality due to defect termination at the sidewalls. Simultaneously, the thermal strain induced by different thermal expansion parameters of GaAs and Si is fully relieved. This opens the route to thick film applications without crack formation and wafer bowing. (C) 2013 AIP Publishing LLC.