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A newer nanoscale technology called quantum-dot cellular automata (QCA) has been used by researchers to design digital circuits in place of the more traditional complementary metal–oxide semiconductor (CMOS) technology. This recent development in the technology change is due to the problems faced by CMOS technology in terms of power consumption and physical limitations. The advantages of QCA technology over CMOS technology are high density, low power consumption, high-speed operation, and less footprint area. This research provides a novel circuit for D-latch and static random access memory (SRAM) cells based on QCA technology. Initially, a D-latch circuit is proposed with a layout area of 0.01 μm2, a 0.5 clock cycle delay (latency), and a cell count of 18 QCA cells. Furthermore, an SRAM cell is proposed using the same D-latch circuit, which uses cell counts of 26 QCA cells and contributes to a layout area of 0.02 μm2 with a 0.75 clock cycle delay (latency). It is observed that our proposed circuits have a smaller layout area, fewer QCA cell counts, and a lower clock cycle delay (latency) than existing circuits. [ABSTRACT FROM AUTHOR]

The power requirements of wireless sensor networks and internet of things (IoT) applications heavily rely on batteries. It is crucial that the memory cells utilized in these applications must consume low-power to prolong the battery life. In this paper, a static-random access memory (SRAM) cell is introduced that incorporates eleven carbon nanotube field-effect transistors (CNTFETs). The proposed 11T CNTFET SRAM cell employs a single-ended approach for reading and writing data and read-decoupled approach to access data in the bit cell. In addition to this, Schmitt-trigger (ST) inverter is incorporated within the bit cell, to enhance its stability and power efficiency. To evaluate the performance of the proposed 11T CNTFET SRAM cell, 32 nm CNTFET model developed by the Stanford University- and HSPICE simulation tool are used for the simulations. The proposed 11T CNTFET bit cell's results show write power, hold power, read power, write static noise margin, hold static noise margin read static noise margin, write delay and read delay of 0.182 nW, 0.2 nW, 0.197 nW, 453.5 mV, 380.5 mV, 383.3 mV, 102 pS and 41.9 pS, respectively at VDD = 0.9 V. Comprehensive parametric simulations are also carried out to analyze the impact of various CNTFET parameters on performance metrics of proposed SRAM cell. The performance of proposed SRAM is fairly compared with existing SRAM cells implemented with CNTFETs and results are found to be quite encouraging. The proposed SRAM cell finds its suitability for use in designing memory devices targeted for wireless sensor networks, Internet of Things and smart biomedical gadgets. [ABSTRACT FROM AUTHOR]

As memories dominate the system-on-chip (SoC), their quality significantly impacts the chip manufacturing yield. There is a growing need to reduce the chip production time and cost, which mainly depends on the testing phase. Hence, a memory built-in self-test (MBIST) utilizing a low-complexity, high-fault-coverage test algorithm is essential for efficient and thorough memory testing. The March AZ1 algorithm, with 13N complexity, was created earlier to balance the test length and fault coverage. However, poor positioning of a write operation in its test sequence caused the reduction of the transition coupling fault (CFtr) detection. This paper presents the creation of the March AZ algorithm, modified from the March AZ1 algorithm, to increase CFtr coverage while preserving the same complexity. It was accomplished by analyzing the fault coverage offered by the March AZ1 algorithm and then reorganizing its test sequence to address the limitation in detecting CFtr. The newly produced March AZ1 algorithm was successfully implemented in an MBIST controller. The simulation tests validated its functionality and demonstrated that the CFtr coverage was enhanced from 62.5% to 75%, achieving an overall fault coverage of 83.3%. Therefore, with 13N complexity, it offers the best fault coverage among all the existing test algorithms with a complexity below 18N. [ABSTRACT FROM AUTHOR]

The 8T static random-access memory (SRAM) cell using carbon nanotube technology, positive feedback, and dynamic supply voltage scaling are presented in this work. Positive feedback strengthens the feedback loop and enhances the noise margin making SRAM cells less susceptible to disturbance and improving the stabilization of the cell by improving read and write timing response. Positive feedback control (PFC) adjusts the cell's operating condition based on its current and external condition under varying conditions. The positive power supply controlled (PPC) technique in SRAM cell design improves the stability and leakage power consumption by adjusting the voltage level during the operation mode of the cell. The experiment with carbon nanotube field-effect transistor (CNTFET) offers higher drive current and lower power consumption compared to conventional silicon-based transistors. The performance of the 8T SRAM cell incorporating PFC and PPC transistor is investigated with Synopsys HSPICE using the Stanford CNFET model. The proposed SRAM cell architecture archives a 99.99% improvement in power consumption and delay product (PDP) compared to a conventional 6T SRAM cell. The static noise margin of 300 mV ensures better noise immunity and reliable retention of data. The mean value of power consumption is 43.19 nW showing a variance of 93.16 fW and a standard deviation (σ) of 305.2 nW and the mean value of delay is 14.71 ps showing a variance of 1.010 and a standard deviation (σ) of 10.05 ps. CNTFET 8T SRAM cell with the combination of positive feedback and dynamic feedback enhances the performance and efficiency of the memory cell under varying conditions. [ABSTRACT FROM AUTHOR]

As CMOS technology has advanced, the transistor integration density of static random-access memory (SRAM) cells has increased. This has led to a reduction in the critical charge of sensitive nodes, making the SRAM cells more susceptible to soft errors. When high-energy particles in space strike the sensitive nodes of an SRAM cell, a single-event upset (SEU) can occur, altering the stored data. Additionally, the charge-sharing effect between transistors can cause single-event multi-node upsets (SEMNUs). To address these challenges, this paper proposes a radiation-hardened 16T SRAM cell optimized for stability and power, referred to as RHSP16T. The performance of the proposed RHSP16T cell was compared with other radiation-hardened SRAM cells, including QUC-CE12T, WE-QUATRO, RHBD10T, RHD12T, and RSP14T. Simulation results indicate that the proposed RHSP16T cell exhibits higher read and write stability, along with lower-leakage power consumption. compared with all other cells. This demonstrates that RHSP16T ensures high reliability for stored data. Furthermore, EQM results show that the RHSP16T cell outperformed the compared designs in overall SRAM cell performance. The proposed integrated circuit was implemented in a 90 nm CMOS process and operated on 1 V supply voltage. [ABSTRACT FROM AUTHOR]

The seamless handover of mobile devices is critical for maximizing the potential of smart city applications, which demand uninterrupted connectivity, ultra-low latency, and performance in diverse environments. Fifth-generation (5G) and beyond-5G networks offer advancements in massive connectivity and ultra-low latency by leveraging advanced technologies like millimeter wave, massive machine-type communication, non-orthogonal multiple access, and beam forming. However, challenges persist in ensuring smooth handovers in dense deployments, especially in higher frequency bands and with increased user mobility. This paper presents an adaptive handover management scheme that utilizes reinforcement learning to optimize handover decisions in dynamic environments. The system selects the best target cell from the available neighbor cell list by predicting key performance indicators, such as reference signal received power and the signal–interference–noise ratio, while considering the fixed time-to-trigger and hysteresis margin values. It dynamically adjusts handover thresholds by incorporating an offset based on real-time network conditions and user mobility patterns. This adaptive approach minimizes handover failures and the ping-pong effect. Compared to the baseline LIM2 model, the proposed system demonstrates a 15% improvement in handover success rate, a 3% improvement in user throughput, and an approximately 6 sec reduction in the latency at 200 km/h speed in high-mobility scenarios. [ABSTRACT FROM AUTHOR]

SRAM is crucial in cryptographic devices for temporarily storing secret keys used in encryption and decryption. However, conventional 6T SRAM cells are vulnerable to side-channel attacks (SCA) via power consumption analysis, as writing the same and opposite data consumes unequal power. Additionally, the Negative Bias Temperature Instability (NBTI) effect in PMOS transistors introduces a data imprinting attack, where attackers exploit differences in the relative strength of pull-up transistors, affecting the threshold voltage (Vth), noise margin (SNM), and delay of the SRAM cell, to retrieve stored data. To address these vulnerabilities, a new SRAM cell design is proposed, incorporating a loop cutting technique to prevent SCA and data toggling behavior to mitigate the data imprinting attack. Monte Carlo simulations of power dissipation during various write operations show that the proposed cell achieves a secure write operation with a maximum overlap of 96.87%. The loop cutting technique reduces power dissipation by 1.54 times and write operation time by 1.44 times compared to the conventional 6T SRAM cell. The stress factor (SF) is also calculated to measure the stress on storage nodes over time. The SF for the 6T SRAM cell is 2.34 after 180 min, while the data toggling approach in the proposed SRAM cell achieves an SF of 0.72, effectively preventing the data imprinting effect. The introduction of transmission gates increases the area overhead of the proposed cell by 1.88×. All simulations are conducted using the gpdk 90-nm technology file in Cadence Virtuoso. [ABSTRACT FROM AUTHOR]

The performance of Static Nanomaterials Random-Access Memories (SRAMs) is often degraded in the sub-threshold region as it is susceptible to increased access energy and leakage power. However, the low-power operation of SRAM is very much essential for efficient device functioning. Accordingly, designing robust SRAM cells that maintain stability and minimize power consumption is a key challenge. In this regard, with this ongoing work, the authors present novel designs of SRAMs using memristor technology by mitigating the shortcomings discussed above. This paper proposes a novel SRAM architecture of four transistors and five memristors, by integrating memristor technology to achieve drastic improvement in performance at subthreshold regions. Further, it performs an analysis of the metrics of static noise margin and power consumption to comprehensively evaluate the proposed SRAM designs. Simulation using Cadence Virtuoso for 65 nm technology demonstrates that power consumption for a 4T5M cell is about two and a half times lower than for 4T4M and 1.2 times lower than for 4T3M, hence proving that it will be promising for extremely low-power applications. [ABSTRACT FROM AUTHOR]

The critical charge of sensitive nodes decreases as transistors scale down with the advancement of CMOS technology, making SRAM cells more susceptible to soft errors in the space industry. When a radiation particle strikes a sensitive node of a conventional 6T SRAM cell, a single event upset (SEU) can occur, flipping in the stored data in the cell. Additionally, charge sharing between transistors can cause single-event multi-node upsets (SEMNUs), where data in multiple nodes are flipped simultaneously due to a single particle strike. Therefore, this paper proposes a radiation-hardened high stability 16T (RHHS16T) cell for space applications. The characteristics of RHHS16T are evaluated and compared with previously proposed radiation-hardened SRAM cells such as QUCCE12T, WEQUATRO, RHBD10T, RHD12T, RSP14T, RHPD14T, and RHBD14T. Simulation results for RHHS16T indicated that the proposed cell demonstrates improved performance in read stability, write access time, and write stability compared to all comparison cells. These improvements in the proposed cell are achieved with higher power consumption and a minor area penalty. Notably, isolating the storage node from the bit line during read operations and the feedback loop between nodes during write operations enables the proposed RHHS16T to achieve enhanced read stability and write stability, respectively. The proposed integrated circuit was implemented using a 90 nm CMOS process and operates at a supply voltage of 1V. Furthermore, RHHS16T provides high immunity against SEUs and SEMNUs. Through its enhanced read and write stability, it ensures reliable data retention for space applications. [ABSTRACT FROM AUTHOR]

In this work, a transmission gate-based low-power ten FinFET (TGLP10T) single-ended read/write SRAM cell is proposed. The proposed cell achieves low leakage operation along with improved write-ability. The performance metric results obtained from TGLP10T are compared with five previously published bit-cell designs, i.e., conventional 6T (Con6T), robust transmission gate-based 10T SRAM (RTG10T), transmission gate-based variation resistant 9T SRAM (TGVR9T), PNN (PMOS-NMOS-NMOS) inverter-based 10T (PNN10T) and PPN (PMOS-PMOS-NMOS) inverter-based read decoupled 10T (PPNRD10T. The leakage power in proposed design is reduced by 1.27×∕1.15×∕1.33×∕1.15×∕1.00× compared to Con6T/RTG10T/TGVR9T/PNN10T/PPNRD10T cells. The write power and WSNM are improved by 1.07×∕1.40×∕0.87×∕1.63×∕0.78× and 1.57×∕1.69×∕1.08×∕1.59×∕1.50×∕1.00×, respectively, compared to Con6T/RTG10T/TGVR9T/PNN10T/PPNRD10T cells. The read delay and write delay are improved by 1.00×∕1.54×∕1.36×∕1×∕2.83× and 1.68 ×∕2.35×∕1.82×∕2.89×∕1.77×, respectively, compared to Con6T/RTG10T/TGVR9T/PNN10T/PPNRD10T cells. The proposed design shows the least data retention voltage compared to other SRAM bit-cells. [ABSTRACT FROM AUTHOR]

As the progress of technology continues in accordance to Moore's law, the density and downsizing of circuitry presents a significant vulnerability to the effects of soft errors. This study proposed a novel method to mitigate soft errors by increasing the robustness of complementary metal oxide semiconductor (CMOS) technology against soft errors via the use of transmission gates within the memory nodes of static random access memory (SRAM) which functioned as a low pass filter that disallowed the occurrence of data corruption. The proposed SRAM was tested against parameter variation of supply voltage and temperature. The critical charge was observed to increase with supply voltage increase, with the opposite being true of the increase in temperature. The increase in critical charge of up to 88.63% was achieved with regards to parameter variation for the transmission gate SRAM in comparison to the 6T SRAM. [ABSTRACT FROM AUTHOR]

The increasing demand for high-performance and low-power hardware in artificial intelligence (AI) applications, such as speech recognition, facial recognition, and object detection, has driven the exploration of advanced memory designs. Convolutional neural networks (CNNs) and deep neural networks (DNNs) require intensive computational resources, leading to memory access times and power consumption challenges. To address these challenges, we propose the application of computing-in-memory (CIM) within FinFET-based 8T SRAM structures, specifically utilizing P-latch N-access (PLNA) and single-ended (SE) configurations. Our design significantly reduces power consumption by up to 56% in the PLNA configuration and 60% in the SEconfiguration compared to traditional FinFET SRAM designs. These reductions are achieved while maintaining competitive delay performance, making our approach a promising solution for implementing efficient and low-power AI hardware. Detailed simulations in 7 nm FinFET technology underscore the potential of these CIM-based SRAM structures in overcoming the computational bottlenecks associated with DNNs and CNNs. [ABSTRACT FROM AUTHOR]

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In space environments, radiation particles affect the stored values of SRAM cells, and these effects, such as single-event upsets (SEUs) and single-event multiple-node upsets (SEMNUs), pose a threat to the reliability of systems used in the space industry. To mitigate the impacts of SEUs and SEMNUs, this paper proposes the Read Stability Improved and Low Power (RSLP16T) SRAM cell. It was confirmed that in SEU-induced simulations, all nodes of the RSLP16T could be restored with a charge amount of less than 100 fC. Additionally, it was verified that a similar level of restoration was possible for SEMNUs occurring in pair of storage nodes. The proposed cell achieves a high level of read stability due to a high pull-down cell ratio (current ratio, CR) at the storage nodes and the fact that only a pair of nodes is in contact with the bit lines during read operations. Because all node paths use a stacking structure for internal transistor configuration and a relatively higher number of cells are composed of PMOS, it consumes the least hold power. While these improvements come at the cost of slightly increased delay time and area, performance evaluation revealed that the equivalent quality metric (EQM) was the highest, indicating that the benefits outweigh the drawbacks. The proposed integrated circuit is implemented in the 90 nm CMOS process and operated on 1 V supply voltage. [ABSTRACT FROM AUTHOR]

The traditional Von Neumann architecture creates bottlenecks due to data movement. The compute-in-memory (CIM) architecture performs computations within memory bit-cell arrays, enhancing computational performance. Edge devices utilizing artificial intelligence (AI) address real-time problems and have established themselves as groundbreaking technology. The 8T structure proposed in this paper has strengths over other existing structures in that it better withstands environmental changes within the SRAM and consumes lower power during memory operation. This structure minimizes reliance on complex ADCs, instead utilizing a simplified voltage differential approach for multiply-and-accumulate (MAC) operations, which enhances both power efficiency and stability. Based on these strengths, it can achieve higher battery efficiency in AI edge devices and improve system performance. The proposed integrated circuit was simulated in a 90 nm CMOS process and operated on a 1 V supply voltage. [ABSTRACT FROM AUTHOR]

FeFET architectures for non‐volatile on‐chip memory are designed and compared in this investigation study. Because of its inherent non‐volatile properties and low power requirements, FeFETs are attracting a lot of interest as prospective candidates for future memory technology. The aim of this paper is to investigate several FeFET designs and assess how well they function in terms of important factors including durability, retention, speed, and endurance. Using device simulations and experimental data, a number of FeFET architectures, such as MFS, MFIS, MFMIS, and MF‐ABO3, are analyzed and contrasted. Comparative study gives light on the advantages and disadvantages of various FeFET architectures; improving our comprehension of how well‐suited they are for non‐volatile on‐chip memory. This work will contribute to the improvement of FeFET devices for upcoming integrated circuits and progress the development of sophisticated FeFET‐based memory techniques. [ABSTRACT FROM AUTHOR]

This work presents a FinFET‐based stable, and low‐power consuming static random access memory (SRAM) bit‐cell that used eight transistors. The performance parameter of proposed feedback‐cutting 8T (FC8T) is compared with four pre‐published cell circuits, i.e., 6T, read‐decoupled 8T(8TRD), Schmitt‐trigger based 10T (10TST), and Schmitt‐trigger‐based modified 10 T (10TMST). The write power in proposed design is reduced by 1.36×/1.32×/1.88×/1.47× compared to 6T/8TRD/10TST/10TMST cells. The write and read stability of proposed design is improved by 1.15×/1.86×/1.28×/1.148× and 2.27×/1×/1.57×/1.11×, respectively. The proposed design also shows the low variability compared to other SRAM bit‐cells. [ABSTRACT FROM AUTHOR]

In wireless sensor networks, conserving power is vital for prolonging battery life. This research introduces a groundbreaking solution: a 9T carbon nanotube‐field effect transistor (CNTFET) based SRAM cell (9T SRAM) designed to optimize power consumption and stability. Through meticulous analysis, the performance of this 9T SRAM cell is quantified. Power consumption metrics reveal impressive figures: the write, hold, read, and dynamic power are measured at 0.21 nW, 0.32 nW, 15.28 μW, and 8.09 μW, respectively. Furthermore, the Write SNM (WSNM), Hold SNM (HSNM), and Read SNM (RSNM) are found to be 380.11, 390.22, and 390.31 mV, respectively, indicating robust stability. The proposed bit cell has a write and read delay of 95.1 and 39.6 pS, respectively. Incorporating stacked transistors diminishes power consumption, while the decoupled read technique boosts the stability of the proposed bit cell. By comparing these results with existing SRAM cells, the superiority of the proposed 9T SRAM cell in terms of power efficiency becomes evident. Notably, it outperforms earlier models, making it an ideal candidate for integration into wireless sensor networks. These findings are supported by simulations conducted using HSPICE, alongside a 32 nm CNTFET model sourced from Stanford University. [ABSTRACT FROM AUTHOR]

This paper aims to propose a novel method for designing an static random access memory (SRAM) cell using an etched drain based Cyl GAA TFET with a hetero‐substrate material and an elevated density strip. The aim is to reduce power dissipation and improve stability, as demonstrated through analysis utilizing static noise margin (SNM) as well as N‐curve methods. With respect to the 16 nm MOSFET based SRAM cell, the proposed device‐based SRAM cell shows significant improvements with a 68.305% reduction in leakage power, a 15.58% increase in static voltage noise margin (SVNM), an 8.623% increase in static current noise margin (SINM), an 8.152% increase in write trip voltage (WTV), a 12.86% increase in write trip current (WTI), a 27.62% increase in static power noise margin (SPNM), and a 19.95% increase in write trip power (WTP). The design is implemented and analyzed using Cadence Virtuoso software, and a novel approach of look up tables and Verilog A is utilized for the device to circuit application. These results indicate promising advancements in the design of SRAM cells, which could have significant implications for the development of advanced computer systems. [ABSTRACT FROM AUTHOR]

Featured Application: Protection and encryption of digital files using hardware fingerprinting. Using an XOR Gate, two Static Random-Access Memory (SRAM) PUFs' challenge–response pairs (CRPs) can be combined into a single larger SRAM PUF. This study focuses on designing enhanced Physically Unclonable Functions (PUFs) based on SRAM devices and improving the security of cryptographic systems. Most SRAM PUFs are limited in their number of CRPs, which makes them vulnerable to enrollment attacks. In this research, we present an SRAM-based PUF design that greatly increases the number of CRPs and the entropy of the generated bits by performing exclusive-or (XOR) on the responses of two SRAM devices. This was implemented using a readily available development board, SRAM devices, and a user-friendly custom circuit board for cryptographic key generation. The cryptographic protocol was implemented using both C++ and python3. The proposed SRAM PUF design was experimentally demonstrated and showed substantial improvements in the security of various cryptographic applications as a hardware authentication device. It also addresses the specific vulnerabilities of legacy designs. [ABSTRACT FROM AUTHOR]

SRAM reliability is one of the major concerns as it suffers from variations in Static Noise Margin with temperature variations, which degrades the performance. It needs attention due to the increasing impact of process corners, which are variations in parameters due to the switching properties of transistors. Since the SRAM is also used as in-memory computation, stability plays a significant role in the computation. In this manuscript, 8T-SRAM stability for NOR, NAND logic is presented at process corners: Fast NMOS-Fast PMOS (FF), Fast NMOS-Slow PMOS (FS), and Slow NMOS-Slow PMOS (SS), with changes in temperature and monte-carlo simulations are also performed to predict the probability of Read Bit Line (RBL) voltage. The results are obtained using Cadence Virtuoso Simulations at the 45 nm technology node and show that the RBL voltage deviates by 10–30 mV for every 25°C rise in temperature from −25oC to 125oC. [ABSTRACT FROM AUTHOR]

This paper presents a single-ended 12-transistor SRAM cell capable of operating at near-threshold voltage in FinFET technology. This cell employs Schmitt trigger-based inverters and feedback cut write assist technique to improve performance properties. The simulations have been done through HSPICE using 10 nm FinFET technology at a supply voltage of 0.45 V and a temperature of 25°C under 5000 Monte Carlo tests. The proposed cell improves the read static noise margin by at least 1.01 times. The write static noise margin is also increased by at least 1.07. The proposed single-ended cell leads to a reduction of $ {\alpha _{BL}} $ αBL by 50% and offers low dynamic write power. The leakage power is also reduced by 1.03 times due to the use of single bitline in the cell structure, stack transistors in the write path and elimination of leakage in the read path. [ABSTRACT FROM AUTHOR]

The ubiquitous smart meters are expected to be a central feature of future smart grids because they enable the collection of massive amounts of fine-grained consumption data to support demand-side flexibility. However, current smart meters are not smart enough. They can only perform basic data collection and communication functions and cannot carry out on-device intelligent data analytics due to hardware constraints in terms of memory, computation, and communication capacity. Moreover, privacy concerns have hindered the utilization of data from distributed smart meters. Here, we present an end-edge-cloud federated split learning framework to enable collaborative model training on resource-constrained smart meters with the assistance of edge and cloud servers in a resource-efficient and privacy-enhancing manner. The proposed method is validated on a hardware platform to conduct building and household load forecasting on smart meters that only have 192 KB of static random-access memory (SRAM). We show that the proposed method can reduce the memory footprint by 95.5%, the training time by 94.8%, and the communication burden by 50% under the distributed learning framework and can achieve comparable or superior forecasting accuracy to that of conventional methods trained on high-capacity servers. Smart meters collect detailed consumption data but struggle with on-device analytics due to hardware and privacy issues. The authors propose an end-edge-cloud federated split learning framework to introduce edge intelligence, reducing memory, training time, and communication burden while maintaining accuracy. [ABSTRACT FROM AUTHOR]

The switching speed and driving capability have been enhanced by scaling the transistor size to nanoscale. The limitations in using MOSFET are that the short channel effects such as leakage current, subthreshold voltage, etc. thereby the Complementary Metal Oxide Semiconductor (CMOS) scaling is challenging now.This leads to the emergence of multi-gate devices, such as Fin Field Effect Transistor (FinFET) and Double Gate FinFET (DG-FinFET), which reduces the short channel effect. Now, a days memory plays a vital role in Integrated Circuits (IC), so the size of it must be scaled down to reduce the overall leakage andinstead of CMOS an advanced MOSFET such as FinFET can be used to avoid SCE. The area of the memory Static Random Access Memory (SRAM) is reduced by eliminating the two-load transistor. The novel 4T SRAM is designed at 10 nm 0.75 v FinFET Technology and compared with 14 nm Technology that is inbuilt into content addressable memory (CAM) to reduce the power consumption of CAM. The results show that the proposed design improves on a voltage basis and the complexity of the circuit is reduced by about 23% in terms of transistor count compared with the other conventional techniques. The 10 nm FinFET Hybrid Self Controlled - PreCharge Free (HSCPF) CAM design is best-suitable for low-power applications. [ABSTRACT FROM AUTHOR]

Wearable device applications such as smartwatches, fitness trackers, and health monitors rely on batteries for power and require static random-access memory (SRAM) with low power consumption and high stability to ensure accurate sensor readings during prolonged operation. In this regard, this paper proposes a novel low-power single-ended 10-transistor (SE10T) SRAM cell with high stabilities. It utilises a stacked pull-down structure for hold/read stability improvement and leakage power reduction, a feedback-cutting mechanism for writability enhancement, and single-ended read/write structures for dynamic power reduction. Also, using a single-transistor reading path with eliminated read bitline leakage enhances ON-to-OFF currents (ION/IOFF) ratio. The proposed design is compared with the conventional 6T, Schmitt-trigger 10T (ST10T), differential writing 10T (DW10T), data-independent read port 10T (DIRP10T), transmission gate read-decoupled 9T (TGRD9T), and feedback-cutting 11T (FC11T) SRAM cells based on 7-nm Fin-shaped Field-Effect Transistor (FinFET) technology at VDD = 0.4 V. The proposed design shows at least 1.04×/1.01×/1.12×/1.25×/1.15× improvement in read stability/writability/read delay/leakage power/dynamic power. Moreover, it shows at least 1.22× improvement in ION/IOFF ratio and offers the lowest minimum operating voltage (0.292 V). However, it offers a 1.02× lower hold stability than that of ST10T, a 1.18×/1.14×/1.13× higher write delay compared to 6T/ST10T/DW10T, and a 1.56×/1.07×/1.05× higher layout area occupation in comparison with 6T/TGRD9T/DIRP10T. Therefore, the proposed SRAM cell can be an optimum candidate for usage in smartwatches. [ABSTRACT FROM AUTHOR]

This research introduces a proposed energy-efficient radiation-hardened and improved read stability (RHIRS)-12T SRAM cell with a polarity hardening technique, which lowers the vulnerable nodes and allows all single-event upset (SEU) techniques to recover from single-event multiple-effect (SEME). To evaluate the relative performance using UMC 65nm CMOS technology of the proposed cell, a comparison analysis is conducted with various radiation-hardened SRAM cells currently in use, such as RHPD-12T, RHWC12T, HPHS12T, RHBD12T, RHD-12T, and EDP12T. When compared to the existing 12T SRAM cells, the proposed RHIRS-12T radiation-hardened SRAM cell has the highest read and hold stability. Compared to EDP12T, RHPD-12T, and RHWC12T SRAM cells, the simulation results demonstrate improvements in write delay of 33.63%, 21.41%, and 9.58%, respectively. It exhibits the lowest read delay as compared to the other considered SRAM cells. It saves 76.34%, 43.68%, 2.77%, and 0.13% energy consumption compared with RHBD12T, HPHS12T, RHPD-12T, and RHWC12T, respectively, during the read operation and it also saves 55.59%, 21.44%, and 6.04% energy compared with EDP12T, RHD-12T, and RHWC12T, respectively, during the write operation. It also shows enhancements of 78.55%, 61.06%, 44.87%, 20.11%, and 0.12% in critical charge value compared to RHBD12T, HPHS12T, RHWC12T, RHPD-12T, and RHD-12T, respectively. Additionally, we evaluate the relative performance of the proposed RHIRS-12T, a comparison analysis is performed with RHD-12T radiation-hardened SRAM cells having low-voltage transistor (LVT), standard-voltage transistor (RVT or SVT), high-voltage transistor (HVT), and super-high voltage transistor (SHVT). It exhibits the highest improvement in read stability at LVT compared to RHD-12T SRAM cell. It can also be used for aerospace applications due to its improved performance and stability. [ABSTRACT FROM AUTHOR]

Binary neural networks (BNNs) that use 1-bit weights and activations have garnered interest as extreme quantization provides low power dissipation. By implementing BNNs as computation-in-memory (CIM), which computes multiplication and accumulations on memory arrays in an analog fashion, namely, analog CIM, we can further improve the energy efficiency to process neural networks. However, analog CIMs are susceptible to process variation, which refers to the variability in manufacturing that causes fluctuations in the electrical properties of transistors, resulting in significant degradation in BNN accuracy. Our Monte Carlo simulations demonstrate that in an SRAM-based analog CIM implementing the VGG-9 BNN model, the classification accuracy on the CIFAR-10 image dataset is degraded to below 50% under process variations in a 28 nm FD-SOI technology. To overcome this problem, we present a variation-aware BNN framework. The proposed framework is developed for SRAM-based BNN CIMs since SRAM is most widely used as on-chip memory; however, it is easily extensible to BNN CIMs based on other memories. Our extensive experimental results demonstrate that under process variation of 28 nm FD-SOI, with an SRAM array size of 128 × 128 , our framework significantly enhances classification accuracies on both the MNIST hand-written digit dataset and the CIFAR-10 image dataset. Specifically, for the CONVNET BNN model on MNIST, accuracy improves from 60.24% to 92.33%, while for the VGG-9 BNN model on CIFAR-10, accuracy increases from 45.23% to 78.22%. [ABSTRACT FROM AUTHOR]

The article explores the roadmap to neuromorphic computing with a focus on emerging technologies, challenges, and potential solutions in the field. It discusses the significance of materials engineering, various approaches to neuromorphic research, and the importance of balancing performance with sustainability. The text also delves into the potential of 2D-LMs in mimicking synapses and neurons in artificial neural networks, highlighting the stable resistive switching observed in certain materials. Efforts are ongoing to address challenges and further advance the use of 2D-LMs in neuromorphic computing, offering promising solutions to computational challenges faced by traditional digital computers. [Extracted from the article]

With the advancement of CMOS technology, the susceptibility of SRAM to single node upset (SNU), double node upset (DNU), and multiple node upset (MNU) induced by radiation has increased. To address this issue, various cutting-edge solutions, such as radiation hardened sextuple cross coupled (RHSCC)-16T and DNU-completely-tolerant memory (DNUCTM) cells, have been proposed. While the RHSCC-16T cell is robust against SNU, it may be vulnerable to DNU. The DNUCTM cell is resistant to both SNU and DNU, but it remains susceptible to MNU. In this paper, we propose a radiation hardened read-stability and speed enhanced (RHRSE)-20T SRAM, which is immune to all potential cases of SNU, DNU, and MNU. Additionally, the proposed design demonstrates improvements in read and write delays compared to conventional SRAM designs. Experimental results confirm that the RHRSE-20T SRAM maintains stability under various charge levels for SEU, DNU, and MNU. The proposed integrated circuit is implemented in a 90-nm CMOS process and operates on a 1 V supply voltage, offering significant advantages for next-generation radiation-hardened memory applications. [ABSTRACT FROM AUTHOR]

The effect of single event transient (SET) on 6T SRAM cell employing a 20 nm silicon‐based junctionless tunneling field effect transistor (JLTFET) is explored for the first time. JLTFET‐based SRAM circuit is designed using the look up table‐based Verilog A code obtained from TCAD values of the device. After verifying SRAM circuit for its functionality, the stability parameters, read static noise margin (RSNM), write static noise margin (WSNM), read/write delay, and power consumption are evaluated. It is observed that the circuit has a good stability of noise margin and lesser delay. The radiation study is carried out using a transient current source striking at one of the output nodes. This causes single event upset (SEU) which changes the data stored in the memory cell giving rise to soft error (SER). SER is recovered by the radiation hardening by design (RHBD) technique with an additional RC network between two cross coupled inverters. The performance metrics, read/write delay, and the power consumption before, during, and after the radiation strike are analyzed. It is observed that SER gets totally eliminated with less recovery time at the expense of a slight increase in power and delay. [ABSTRACT FROM AUTHOR]

With the development of processes and reduction of transistor size, transistor sensitivity to voltage changes has increased. Traditional SRAM bit cells struggle to function properly at low voltages, and the lengthy write time necessitated by the write conflict problem will inevitably result in write failure. As ultra‐low‐voltage SRAM has emerged as a significant direction of research for SRAM, this paper proposes an ultra‐low‐voltage 9T SRAM bit cell that is conflict‐free. By circumventing write conflicts and enabling rapid writing, the bit cell demonstrates its superiority, particularly at ultra‐low voltages, by eliminating the requirement for peripheral write‐assist circuitry to accomplish chip writing. To assess the performance of the conflict‐free 9T bit cell, simulation experiments are conducted utilizing the 28 nm process model. Simulation results indicate that the 9T bit cell proposed in this paper requires only 66% of the writing time of the traditional 6T cell. This enables the cell to accomplish fast writing and more stable writing performance. [ABSTRACT FROM AUTHOR]

Today’s era is a digital world where each and every section of the society is experiencing and encountering with semiconductor chips. In very large-scale integration (VLSI) circuits the design of static random-access memory (SRAM) plays a crucial role in ensuring both low-power consumption and high-speed performance. The sense amplifiers (SA) are integral parts for information accessing storage in SRAM IC design. This paper introduces a dual voltage latch sense amplifier (DVLSA) for SRAM integrated circuits (IC). The comparative analyses of various SA are studied and then design a low-power SA through the implementation of energy-efficient technique. Further, we have elucidated the causes of delay and power dissipation in different SA with useful solutions and performance evaluation is conducted by comparing the proposed design with existing SA reported in the literature. The performance parameters such as power 1.604 uw, energy 470.50 fJ, delay 80.04 ps, and current 5.406 are scrutinized to assess the efficiency of the designs. The cell outcomes have been validated with cadence tool on 180 nm technology and operate at 1.8 V. The proposed design, namely, DVLSA demonstrates minimal energy consumption and low power dissipation, making it a promising advancement in SRAM IC technology. [ABSTRACT FROM AUTHOR]

The conventional planar Metal-Oxide-Semiconductor FETs (MOSFETs) are being replaced with Fin Field-Effect Transistors (FinFETs) due to their improved ability to manage power dissipation, propagation delay, leakage current, and short channel effects. Process variability is an issue for planar MOSFETs, however the amount of dopant ions in FinFETs reduces device performance variability. In this study, a Static-Random Access Memory (SRAM) cell employing FinFET technology is designed using three MOS transistors. It is composed of two NMOS plus a single PMOS transistor. One NMOS acts as access transistor while the pull-up and pull-down functions are performed by remaining NMOS and PMOS transistors, respectively. The proposed SRAM cell is simulated using H-SPICE simulator and is compared with existing SRAM cell designs in terms delay, power consumption and transistor count. Performance analysis shows that the proposed SRAM Cell overcomes the constraint and achieves full swing storage of logic values between 0 and 1. This justifies the definition of static. Implementing a single-ended SRAM cell also has the benefit of simplifying the SRAM cell architecture, which also results in a reduction in area. [ABSTRACT FROM AUTHOR]

A mixed-signal binarized neural network (BNN) processor for the MNIST image classification is demonstrated based on analogue circuit networks. BNN algorithm for training neural networks with binary weights and activations reduces power consumption and memory size. This algorithm is a design to perform core operations of multi-layer perceptron (MLP) to reduce complexity and power consumption using analogue circuits. The mixed-signal BNN processor employs a current mirror neuron to perform multiply-and-accumulate (MAC) operations and sign activation functions. The near-threshold current mirror neuron that computes the key operations of the BNN algorithm is used to achieve low power consumption. The design occupies 0.065 mm2 in 28-nm CMOS with 560B of on-chip SRAM. The 28-nm CMOS test-chip achieves energy efficiency of 24.1 TOPS/W and 94% accuracy on the MNIST image classification. This design with binary weights and activations exhibits only 5% degradation in accuracy compared with the models with floating-point precision. [ABSTRACT FROM AUTHOR]

The exposure of spaceborne devices to high-energy charged particles in space results in the occurrence of both a total ionizing dose (TID) and the single-event effect (SEE). These phenomena present significant challenges for the reliable operation of spacecraft and satellites. The rapid advancement of semiconductor fabrication processes and the continuous reduction in device feature size have led to an increase in the significance of the synergistic effects of TID and SEE in static random access memory (SRAM). In order to elucidate the involved physical mechanisms, the synergistic effects of TID and single-event upset (SEU) in a new kind of 130 nm 7T silicon-on-insulator (SOI) SRAM were investigated by means of cobalt-60 gamma-ray and heavy ion irradiation experiments. The findings demonstrate that 7T SOI SRAM is capable of maintaining normal reading and writing functionality when subjected to TID irradiation at a total dose of up to 750 krad(Si). In general, the TID was observed to reduce the SEU cross-section of the 7T SOI SRAM. However, the extent of this reduction was influenced by the heavy ion LET value and the specific writing data pattern employed. Based on the available evidence, it can be proposed that TID preirradiation represents a promising avenue for enhancing the resilience of 7T SOI SRAMs to SEU. [ABSTRACT FROM AUTHOR]

Some applications, such as satellites, require ultralow power and high-radiation resilience. We developed a12Tsoft error-resilient SRAM cell, TA-Quatro, to deliver in-memory computing (IMC) for those applications. Based on our TA-Quatro cell, we implemented an IMC circuit to support binary weights and ternary activations in a single SRAM cell. Our simulation under 28 nm FD-SOI technology demonstrates that the TA-Quatro IMC circuit maintains good IMC stability at a scaled supply of 0.7Vand achieves ternary activation without needing analog-to-digital converters. These advancements significantly enhance the power efficiency of the proposed IMC circuit compared to state-of-the-art works. [ABSTRACT FROM AUTHOR]

The von Neumann architecture is no longer sufficient for handling large-scale data. In-memory computing has emerged as the potent method for breaking through the memory bottleneck. A new 10T SRAM bitcell with row and column control lines called RC-SRAM is proposed in this article. The architecture based on RC-SRAM can achieve bi-directional and operand-controllable logic-in-memory and search operations through different signal configurations, which can comprehensively respond to various occasions and needs. Moreover, we propose threshold-controlled logic gates for sensing, which effectively reduces the circuit area and improves accuracy. We validate the RC-SRAM with a 28 nm CMOS technology, and the results show that the circuits are not only full featured and flexible for customization but also have a significant increase in the working frequency. At VDD = 0.9 V and T = 25 °C, the bi-directional search frequency is up to 775 MHz and 567 MHz, and the speeds for row and column Boolean logic reach 759 MHz and 683 MHz. [ABSTRACT FROM AUTHOR]

The successful implementation of artificial intelligence algorithms depends on the capacity to execute numerous repeated operations, which, in turn, requires systems with high data throughput. Although emerging computing‐in‐memory (CIM) eliminates the need for frequent data transfer between the memory and processing blocks and enables parallel activation of multiple rows, the traditional structure, where each row has only one identical input value, significantly limits its further application. To solve this problem, this study proposes a dual‐SRAM CIM architecture in which two SRAM arrays are coupled such that all operands are different, thus rendering the use of CIM considerably more flexible. The proposed dual‐SRAM array was implemented through a 55‐nm process, essentially delivering a frequency of 361 MHz for a 1.2‐V supply and energy efficiency of 161 TOPS/W at 0.9 V supply. [ABSTRACT FROM AUTHOR]

Transition metal dichalcogenide field‐effect transistors (TMDFETs) as a replacement for conventional metal–oxide–semiconductor field‐effect transistors (MOSFETs) have attracted the attention of researchers in recent years. The efficiency of these devices should be investigated in different aspects in digital systems. One of the important components of such systems is dynamic random‐access memory (DRAM), which is used in most computers and many electronic systems as the main memory due to its small area and simple structure, compared to static memory (SRAM) cells. In this paper, a regular DRAM cell is designed based on TMDFET devices and its performance is compared with a similar cell in conventional MOSFET technology from various aspects, including DRAM‐specific timing characteristics considering changes in design and environmental parameter variations using Monte Carlo simulations. The simulations have been carried out in HSPICE with 16 nm technology under fair conditions for different technologies, at room temperature with a 0.7‐V power supply. The results show that the TMD‐DRAM has 3.55×, 3.08×, and 2.23× faster bitline recovery, merge time, and sense time than Si‐MOS‐DRAM, respectively. The Si‐MOS‐DRAM, on the other hand, has 1.65× faster write time compared to TMD‐DRAM. However, TMD‐DRAM consumes overall higher power than Si‐MOS‐DRAM, and shows higher average read power variability with the σ/μ = 0.476. The TMD‐DRAM also shows higher variability in the studied timing characteristics than Si‐MOS‐DRAM except merge and sense times. [ABSTRACT FROM AUTHOR]

This paper discusses the stuck bits induced by the gate breakdown of PMOS in the sub-20 nm FinFET static random access memory (SRAM) device. After the heavy-ion experiment, several stuck bits are in the FinFET SRAM matrix, which cannot be set or reset. To investigate the factors that caused the stuck bit, we perform the electrical failure analysis (EFA) to measure the electric characteristics of the transistors in the stuck bits and normal cells separately. The measurement results show a clear gate breakdown at the PMOS pull-up (PPU) transistor in all of the measured SRAM cells. Meanwhile, the SPICE simulation based on the EFA results verifies the impact of the damaged PPU. Finally, considering all of the phenomena, the charge deposition from single events is the major mechanism that causes the stuck bits in FinFET SRAM. The experiment results alert a potential gate breakdown risk in the ultra-high-density FinFET SRAM applied in the space environment. [ABSTRACT FROM AUTHOR]

This paper presents a novel Slumped Static Random-Access Memory (SRAM) configuration utilizing Quantum-dot Cellular Automata (QCA) technology, aimed at achieving enhanced stability and efficiency. Traditional CMOS-based SRAM designs face significant challenges related to power consumption and scalability as technology nodes shrink. QCA, with its potential for ultra-low power dissipation and high-density integration, emerges as a promising alternative. Our proposed SRAM configuration leverages a unique differential voltage sensing mechanism to bolster the stability of the memory cells, particularly under conditions of variability and noise. Through detailed simulations and comparative analysis, we demonstrate that the Slumped SRAM configuration not only improves static noise margin (SNM) but also reduces power consumption and enhances overall read/write speed. The results indicate a substantial improvement in stability and operational efficiency, positioning this design as a viable solution for future high-performance, low-power memory applications. Through detailed simulations and comparative analysis, we demonstrate that the Slumped SRAM configuration achieves a static noise margin (SNM) improvement of 35% over conventional CMOS-based SRAM designs. Additionally, the proposed design reduces power consumption by 40% and enhances read/write speed by 25%. These results indicate a substantial improvement in stability and operational efficiency, positioning this design as a viable solution for future high-performance, low-power memory applications. [ABSTRACT FROM AUTHOR]

Non-invasive side-channel attacks (SCAs) based on leakage power analysis (LPA) have received more attention recently, since leakage current has gradually become more dominant with further scaled technologies. For SRAM cells, LPA exploits the correlation between data in memory cells and their corresponding leakage power. This paper proposes a novel SRAM design in 7 nm node for countering LPA attacks, based on a single-ended PMOS-reading 9T (nine-transistor) cell design. The leakage current imbalance, delay, stability, and robustness of SRAM cells are examined for the proposed memory cell architecture with layout designs, and results are compared against other SRAM cell designs. Simulation results and failure of LPA attacks in case studies confirm the enhanced resilient behavior for the new SRAM cell design. [ABSTRACT FROM AUTHOR]

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In this present scenario, the aggressive scaling affects the working of electronic appliances mostly in Integrated Circuits (IC's) that contains memory which covers almost 65% of that circuitry due to high demand of storage by users the memory size almost covers the 70-80% of the System on Chip (SoC) in International Technology Roadmap for Semiconductor (ITRS) 2015. When we are working on the single bit of any memory cell then that time, the power consumption is miniature level that we can calculate in Pico-watt (pW) or Nano-watt (nW) but as we moves towards the array of memory or kilo byte (kB) then the consumption also increases and reached in micro-watt level. In VLSI industries at lower supply voltage, we can compromise with the technology but we cannot negotiate with the parameters variations mostly in stability, delay and power consumption. The key points are the lowest feature sizes (W/L ratio), lowest power consumption, reduced costs and good stability for designing of any electronic component. This paper emphasis on designing of 4X4 array and single bit of FinFET which based on 10T SRAM Cell and comparison has been done with the CMOS based designing. By 4x4 arrays we can compare the parameters variation from 1 bit to 16 bits and calculated the power consumption, stability and delay at different operating point 0.5, 0.6, 0.7 and 1V and operating mode of write and read mode. [ABSTRACT FROM AUTHOR]

As a green and low-carbon road material, warm-mix rubber asphalt (WMRA) has received extensive attention from scholars for its road performance. In the in-depth study of its properties, the fatigue characteristics of WMRA are particularly critical. However, in current studies on asphalt fatigue performance, its self-healing ability is often underestimated or neglected. Furthermore, the simplified viscoelastic continuum damage theory (S-VECD), with its accuracy, speed, and convenience, provides a powerful tool for analyzing asphalt fatigue performance. Therefore, to analyze the fatigue and self-healing performances of WMRA in practical applications, four sample materials were selected in this study: virgin asphalt mastic (VAM), rubber asphalt mastic (RAM), Sasobit rubber asphalt mastic (SRAM), and Evotherm rubber asphalt mastic (ERAM). Subsequently, the samples were subjected to a comprehensive experimental design with frequency sweep tests, linear amplitude sweep tests, and multiple intermittent loading time sweep tests under different aging conditions. The fatigue and self-healing performances of different aging degrees and different types of WMRA were evaluated based on the S-VECD theory. The results show that aging reduces the fatigue and self-healing performances of asphalt mastic to a certain extent, and at a 7% strain, the fatigue life of SRAM after long-term aging is only 30.7% of the life of the unaged sample. The greater the aging degree, the more pronounced the effect. Under different aging levels, the warm-mix agent can significantly improve the fatigue and self-healing performances of rubber asphalt mastic. After undergoing ten fatigue intermittent loading tests, the recovery rate of the complex shear modulus for the long-term aged VAM was 0.65, which is lower than that of SRAM under the same conditions, and the warm mix can further extend the fatigue life of rubber asphalt by improving the self-healing properties of the asphalt. The role of Sasobit in enhancing the fatigue and self-healing performances of rubber asphalt mastic is more significant. This study can provide a theoretical basis for the promotion and application of WMRA pavements and contribute to the sustainable development of road construction. [ABSTRACT FROM AUTHOR]

The excessive power usage in modern digital equipment is triggered by memory arrays, mainly including Static Random‐Access Memory (SRAM) chips. Many scientists are working to create an SRAM cell that is fast, highly stable, and uses little power. However, the traditional SRAM cells have instability and read/write failure at scaled technology nodes. This study proposes a Differential Power Schmitt‐Trigger Logic 9 Tcompute SRAM (DPSTL‐9 TCSRAM) cell design with high read‐and‐write stability and low energy consumption. In SRAM cells, the sensing amplifier (SA), pre‐charge circuit, row decoder, and column decoder are the primary operational elements. Through the use of a single‐bitline (SBL) configuration and a one‐sided Schmitt‐trigger (ST) inverter (STI), the proposed deisgn cell achieves an outstanding read stability performance. In this work, the differential Power Generation (DPG) technique is employed to improve the architecture's writing capacity. The standard AND gates are combined with Schmitt‐trigger logic AND gates to improve noise tolerance while consuming less power and taking up less space. Instead of using a power‐gating mechanism, this research focuses on modifying a power delay product (PDP) circuit to increase the cell's read‐and‐write operation efficiency. The modified decoupled SA plays a major role in the access time and provides significant benefits in terms of read latency. Tanner EDA Tool platform version 16.0 can be used to execute the specified design. The performance metrics of stability, area, latency, and power analysis are examined, and also, the Monte Carlo simulation and reliability simulation are conducetd to show the efficacy of the proposed design. [ABSTRACT FROM AUTHOR]