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As a high-performance application of low-temperature superconductivity, superconducting single-flux-quantum (SFQ) circuits have high speed and low-power consumption characteristics, which have recently received extensive attention, especially in the field of neural network inference accelerations. Despite these promising advantages, they are still limited by storage capacity and manufacture reliability, making them unfriendly for feedback loops and very large-scale circuits. The Binarized Neural Network (BNN), with minimal memory requirements and no reliance on multiplication, is undoubtedly an attractive candidate for implementing inference hardware using SFQ circuits. This work presents the first SFQ-based Binarized Neural Network inference accelerator, namely JBNN, with a new representation to binarize weights and activation variables. Every SFQ gate is essentially a pipeline stage, making conventional design methods of the accumulator unsuitable for SFQ circuits. So an SFQ-based accumulative parallel counter using SFQ logic cells including T1, OR, and AND is designed to realize the accumulation, where the data size is reduced to a quarter after passing the XNOR column and the AU layer, largely declining the hardware cost. Our evaluation shows that the proposed design outperforms a cryogenic CMOS-based BNN accelerator design running at 77K by 70.92 times while maintaining 97.89% accuracy on the MNIST benchmark dataset. Without the cooling cost, the power efficiency increases up to 929.18 times. [ABSTRACT FROM AUTHOR]

A quantum phase slip junction (QPSJ) based direct inverter gate is proposed in this article for the first time. The proposed inverter is simpler than the QPSJ-based inverter designed indirectly by using a two-input xor gate with specific input conditions. In the indirect inverter, one of the two inputs of the xor gate must be set to the clock pulse in order to perform the true inverter operation. However, the proposed direct inverter has only one input to which the input voltage can be applied directly, and therefore, it has a simpler structure with fewer elements that occupies less area on the chip. The true operation of the proposed inverter is verified by feeding its input with the standard pseudorandom binary sequence 3 and connecting its output to the next gate to test its ability for driving the next gate. [ABSTRACT FROM AUTHOR]

In contrast to transistor-based semiconductor circuits, there is currently no widely accepted formalized circuit theory or design methodology for superconductor rapid single flux quantum (RSFQ) logic circuits. Experienced designers intuitively consider flux loops, nodal phase, and branch currents when making design choices, but the lack of a formalized design process makes it difficult for inexperienced RSFQ circuit designers to construct a functioning logic cell without a reference. This results in new circuit designers, mostly recycling templates from published circuit designs without fully understanding why the circuits function as they do. Inexperienced RSFQ circuit designers often follow an iterative process where cell parameter values are adjusted, and the cell is run through electronic simulation engines until the desired functionality is reached. We propose the development of a formalized circuit design theory for RSFQ logic from first principles using phase-based circuit analysis. The circuit is designed using dc analysis to establish the dc operating point of the circuit. Phase-based analysis and simulation are then used to verify the dynamic circuit functionality. To demonstrate this method, we discuss examples for well-known RSFQ cells. We analyze the initial operating margins of these designs and discuss design accuracy and efficiency. Methods for current regulation to minimize current leakage between cells are discussed. We also present how this design methodology can be used to design new circuits such as an RSFQ XNOR cell. We investigate how an inverting (NOT) cell can be combined with other logic cells to minimize cell latency. [ABSTRACT FROM AUTHOR]

In this article, the quantum phase slip junction (QPSJ) based full adder, multiplexer, and demultiplexer memoryless circuits for superconducting digital applications are designed for the first time. Generally, the memoryless circuits are implemented by interconnection of the basic gates (i.e., AND, OR, NOT). So in this article, the structures of the QPSJ-based AND and OR gates are also modified in order to reduce the complexity of their connections to the other gates by removing or changing the location of the clock pulse from their output branches. When a gate is connected to the next one, the elements of the second gate are loaded to the circuit of the first gate. The output current of the first gate will be affected due to this loading and no Cooper pair may be produced at its output and the next connected gate will not be switched. Therefore, the main tip in designing of these circuits is that each constituent gate must provide the necessary output current to drive the next connected gates, since each gate is driven by one Cooper pair. In this article, providing sufficient output current for each gate has been observed by 1) selecting proper critical voltages of the QPSJs and 2) by adding extra elements to or removing some elements from the connected gates in the proposed memoryless circuits. [ABSTRACT FROM AUTHOR]

Traditional logical equivalence checking (LEC), which plays a major role in the entire chip design process, faces challenges of meeting the requirements demanded by the many emerging technologies that are based on logic models different from the standard complementary metal oxide semiconductor (CMOS). In this article, we propose an LEC framework to be employed in the verification process of superconducting electronics (SCE). Our LEC framework is compatible with the existing CMOS technologies and can also check features and capabilities that are unique to SCE. For instance, the performance of nonresistively biased single-flux quantum (SFQ) circuits benefits from ultradeep pipelining, and verification of such circuits requires new models and algorithms. We, therefore, present the multicycle input dependency circuit model which is a novel model representation of design to explicitly capture the dependency of primary outputs of the circuit on sequences of internal signals and inputs. Embedding the proposed circuit model and several structural checking modules, the process of verification can be independent of the underlying technology and signaling. We benchmark the proposed framework on postsynthesis SFQ and 4-phase adiabatic quantum flux parametron netlists. Results show a comparative verification time of SFQ circuit benchmark, including 16-bit integer divider and ISCAS’85 circuits with respect to the ABC tool for similar CMOS circuits. [ABSTRACT FROM AUTHOR]

With the demand for data processing and storage increasing rapidly, the existing CMOS-based computing system is gradually unable to meet the amplification demand because of its high-power consumption. Due to high frequency and low power consumption, superconducting rapid single-flux-quantum (RSFQ) logic circuit technology is an attractive candidate. In this paper, we propose a novel placement method based on the layer layout. We layer the gates according to the logic level, which is the length of the longest path in terms of the number of clocked gates from any primary input (PI) of the circuit to the gate. Dummy gates are inserted so that any two adjacent layers can form a bipartite graph. Then the gates of each layer are reordered to minimize the half-perimeter wirelength (HPWL). Finally, the gates of each layer are assigned vertical positions to make the edges as straight as possible. The distance between adjacent layers is determined by the number of bending points of the edges between layers. We use several superconducting RSFQ logic circuits to evaluate the effectiveness of our proposed placement method, which uses HPWL and area as evaluation metrics. The experimental results show that compared with the Simulated Annealing (SA)-based placement method, the proposed approach can reduce the total HPWL and total area by an average of 77.77% and 57.56%, respectively. [ABSTRACT FROM AUTHOR]

We have developed a cell library for superconducting large scale integrated (LSI) digital circuits based on Single Flux Quantum (SFQ) devices. The circuits were designed for a 6-kA/cm2 Nb/AlOx/Nb junction process with 10 mask levels including one ground plane and two Nb wiring layers. The initial design and optimization of the circuit parameters were achieved by means of the optimization functions in a circuit simulator, PSCAN2, to ensure that important circuit parameters, Josephson critical current (IC), bias current (Ibias), and inductance satisfied minimal margin requirements. Critical margins of IC and Ibias were then further improved manually. To compensate the scattering in the circuit parameters from fabrication by design as much as possible, the critical junction parameters were optimized to further centralize the IC. The library cells were laid out following our design rules determined by systematic experiments on process control monitors (PCM). Basic cells including Josephson transmission lines, splitters, confluence buffers, D flip-flops, T flip-flops, and XOR and NDRO gates were designed, fabricated, and successfully tested at low frequencies. Wide overlaps of the operating regions for the common bias voltages were confirmed. [ABSTRACT FROM AUTHOR]

RSFQ circuits require a DC bias current to operate properly. The bias current in conventional RSFQ circuits is supplied to each gate, resulting in large current requirements in VLSI complexity SFQ systems, on the order of tens to hundreds of amperes. These high currents are difficult to supply and distribute. Superconductive input/output pins and bias lines support this limited current. Large currents however require significant metal and input pin resources. In addition, large currents can inductively couple to sensitive superconductive inductors, degrading circuit operation and producing errors. Current recycling is a well known technique to reduce these bias currents. RSFQ circuits with similar bias current requirements can be placed on separate ground planes and serially biased. The inputs and outputs of these circuits are galvanically decoupled and require drivers and receivers between connections. In this paper, a methodology for automated partitioning of complex RSFQ circuits into blocks with similar bias currents is described, where the number of connections among the blocks is minimized. Blocks with a significant difference in bias current are balanced using dummy padding structures. These blocks are biased in series, reducing the total bias current by the number of partitions. The Fiduccia-Mattheyses algorithm is modified with RSFQ specific enhancements to partition the system. A geometric partitioning approach, optimized by simulated annealing, is also proposed. These algorithms are integrated into the circuit placement process, and the methodology is evaluated using several modified ISCAS’89 sequential benchmark circuits and the AMD2901. The proposed partitioning methodology is intended for use within an automated EDA flow to enable current recycling for arbitrary (non-uniform, irregular) VLSI complexity RSFQ circuits, drastically reducing overall bias current and input requirements [ABSTRACT FROM AUTHOR]

Single-flux quantum (SFQ) logic based high-speedperiodic-threshold flash converter circuits require multiple non-linear and correlated parameters tuned precisely to function optimally. These parameters cannot be pre-determined from simulations and change with the clock frequency, thus requiring manual optimization every time the clock frequency is changed. In this work, we demonstrate automated bias optimization of an 8-bit superconducting SFQ flash ADC for the first time. A closed-loop 4X lower computational complexity hybrid particle-swarm-gradient-descent-optimization is demonstrated that first uses particle swarm optimization (PSO) to coarse tune the ADC biases and then applies gradient descent (GD) optimization for fine tuning. This results in a 12X reduction in the blind calibration time from several days manually, to a few hours using the proposed optimization scheme, with a resultant performance 2 dB better than an optimization done by a highly skilled human. [ABSTRACT FROM AUTHOR]

A fast Fourier transform (FFT) is an algorithm that computes the discrete Fourier transform (DFT) of a sequence at high speed. FFT can convert a signal from time domain to frequency domain, and is wildly used in digital signal processing field. In this paper, a high-speed, low-power FFT processor is demonstrated up to 47.8GHz with the measured power consumption of 5.3mW, using single-flux quantum (SFQ) logic. This is the first complete FFT processor implementation using superconducting technology, performing 8-point 7-bit FFT in a bit-serial computing manner. The test chip fabricated using a 1.0  μm 9-layer process consists of 17 455 Nb/AlOx/Nb Josephson junctions (JJs), rendering itself the largest superconducting digital circuit capable of iterative data computing. The correct operation of the chip has been experimentally confirmed at a maximum operating frequency of 47.8GHz (word speed 8GHz) by conducting on-chip high-speed testing. [ABSTRACT FROM AUTHOR]

Fault-tolerant quantum computing is required to execute many of the most promising quantum applications. In recent years, numerous error correcting codes, such as the surface code, have emerged which are well suited for current and future limited connectivity 2-D devices. We find quantum memory, particularly resonant cavities with transmon qubits arranged in a 2.5-D architecture, can efficiently implement surface codes with around 20× fewer transmons via this work. We virtualize 2-D memory addresses by storing the code in layers of qubit memories connected to each transmon. Distributing logical qubits across many memories has minimal impact on fault tolerance and results in substantially more efficient logical operations. Virtualized logical qubit (VLQ) systems can achieve fault tolerance comparable to conventional 2-D transmon-only architectures while putting within reach a proof-of-concept experimental demonstration of around ten logical qubits, requiring only 11 transmons and 9 attached cavities. [ABSTRACT FROM AUTHOR]

The superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising solution for the post-Moore era, thanks to the ultrafast and low-power switching characteristics of superconductor devices. Researchers have made tremendous efforts in various aspects, especially in device and circuit design. However, there has been little progress in designing a convincing SFQ-based architectural unit due to a lack of understanding about its potentials and limitations at the architectural level. This article provides the design principles for SFQ-based architectural units with an extremely high-performance neural processing unit (NPU). To achieve our goal, we developed and validated a simulation framework to identify critical architectural bottlenecks in designing a performance-effective SFQ-based NPU. We propose SuperNPU, which outperforms a conventional state-of-the-art NPU by 23 times in terms of computing performance and 1.23 times in power efficiency even with the cooling cost of the 4K environment. [ABSTRACT FROM AUTHOR]

Creating computing systems able to address our ever-increasing needs, especially as we reach the end of CMOS transistor scaling, will require truly novel methods of computing. However, the traditional logic abstractions and the digital design patterns we understand so well have coevolved with the hardware technology that has embodied them. As we look past CMOS, there is no reason to think that those same abstractions best serve to encapsulate the computational potential inherent to emerging devices. We posit that a new and radically more efficient foundation for computing lies at the intersection of superconductor electronics and delay-coded computation. Building on recent work in race logic, we show that superconducting circuits can naturally compute directly over temporal relationships between pulse arrivals; that the computational relationships between those pulse arrivals can be formalized through a functional extension to a temporal predicate logic used in the verification community; and that the resulting architectures can operate asynchronously and describe real and useful computations. We verify our hypothesis through a combination of detailed analog circuit models and layout designs, a formal analysis of our abstractions, and an evaluation of several superconducting temporal accelerators. [ABSTRACT FROM AUTHOR]

We conducted the first successful demonstration of an adiabatic microprocessor based on unshunted Josephson junction (JJ) devices manufactured using a Nb/AlOx/Nb superconductor IC fabrication process. It is a hybrid of RISC and dataflow architectures operating on 4-b data words. We demonstrate register file R/W access, ALU execution, hardware stalling, and program branching performed at 100 kHz under the cryogenic temperature of 4.2 K. We also successfully demonstrated a high-speed breakout chip of the microprocessor execution units up to 2.5 GHz. We use a logic primitive called the adiabatic quantum-flux-parametron (AQFP), which has a switching energy of 1.4 zJ per JJ when driven by a four-phase 5-GHz sinusoidal ac-clock at 4.2 K. These demonstrations show that AQFP logic is capable of both processing and memory operations and that we have a path toward practical adiabatic computing operating at high-clock rates while dissipating very little energy. [ABSTRACT FROM AUTHOR]

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. In this article, we design binary counters, namely an up counter, a down counter, and an up/down counter, based on AQFP logic. These binary counters are T-flip-flop-based and count logic 1s in the input signal that is synchronized with excitation currents, which clock the counters. The internal state of a T flip-flop changes when the internal state of the previous T flip-flop changes from logic 1 to 0 and from logic 0 to 1 for the count-up and count-down operations, respectively. Each internal state of a T flip-flop is read out serially by a buffer chain coupled to the T flip-flops. We fabricate 4-bit up, down, and up/down counters using the AIST 10 kA/cm2 Nb high-speed standard process and demonstrate their correct operation at low frequency. This is the first demonstration of binary counters based on AQFP logic. [ABSTRACT FROM AUTHOR]

In standard single flux quantum (SFQ) logic circuits, it is required to insert path balancing D-flip-flops (DFFs) to guarantee correct circuit operation. DFF insertion should be done in a way that any path from a primary input to a primary output has the same length in terms of the clocked element count. This is known as full path balancing (FPB) method. The FPB method usually requires insertion of many path balancing DFFs that can be even more than the actual gate count in the original circuit. This significantly increases the chip area, lowers the local clock frequency, and increases both static and dynamic power dissipation. This article presents an architecture for realizing SFQ circuits which removes all path balancing DFFs, resulting in a huge reduction in total area, node and Josephson junction count, and power consumption. The drawback is a degradation of the peak throughput of the circuit, which can be overcome by performing partial path balancing in the circuit, thereby recovering the circuit throughput by adding some path balancing DFFs. [ABSTRACT FROM AUTHOR]

We present the results of circuit simulations for the adiabatic flux-operating neuron. The proposed cell with one-shot calculation of activation function is based on a modified single-junction superconducting quantum interferometer. In comparison, functionally equivalent elements of the artificial neural network (ANN) in the semiconductor-based implementations consist of approximately 20 transistors. Also in the article, we present the connecting synapse based on the adiabatic quantum flux parametron. These neurons and synapses allow constructing ANNs with a magnetic representation of information in the form of direction and/or magnitude of the magnetic flux in the superconducting circuit. We discuss the dissipation of energy during operations in the frame of the proposed concept. This value in superconducting neurons and synapses with sub-nanosecond timescale can be reduced down to 10 and 0.1 aJ, respectively. The use of the adiabatic superconducting logic circuits in our approach promises compatibility with superconducting quantum information processing systems. [ABSTRACT FROM AUTHOR]

Switching time limitations of the ac bias current of Josephson junctions in bidirectional rapid single flux quantum (RSFQ) logic circuits are investigated in order to determine the limits to the maximum possible operating frequency. We introduce a new approach based on modifying the bias current parameters and determining the inductance values in the circuit for reducing the switching transition time of the bias current through the junctions. We have simulated and optimized the timing and the operation of the bidirectional nondestructive readout and Josephson transmission line cells in this respect to demonstrate the results of utilizing the proposed approach. We successfully reduced the unwanted spike-type signals across the inductances which are made through the transitions during the fast switching times limiting the operation frequency. This is while we have also removed the consequent destructive spikes at the output. We have included the effects of other determining parameters of the circuit in this investigation and found their relatively optimal values to improve the temporal behavior of the bidirectional RSFQ cells. The results of the proposed approach leading to the fastest possible operation of the considered gates obtained in this work are thoroughly reported. [ABSTRACT FROM AUTHOR]

Accessing multiple data through a common bus in quantum information processing is challenging. Experimental demonstration of quantum state transfer between a pair of superconducting phase qubit [M. A. Sillanpää et al., Nature 449, 438 (2007)] motivates us to construct a scheme for accessing and transferring multi-qubit quantum information through a common cavity bus. Here, we have presented an efficient scheme to access multiple data through single channel using superconducting qubit and superconducting cavity resonator. The qubit-cavity photon coupling offers transfer of quantum data in different location of a quantum processing system from multiple users through a common superconducting cavity resonator. Instead of phase qubit, charge qubit is found to be more advantageous in qubit-cavity interaction for quantum data transformation, because charge qubit is immune to flux and external flux is used to select specific qubit from a set of qubits. The scheme is very generic and provides M-output from N-number of inputs via a common cavity in circuit quantum electrodynamics. The flexibility of the scheme allows us to implement multiplexer, demultiplexer, and so on for quantum data manipulation in a similar manner as in classical digital electronics. This scheme is useful to reduce the circuit complexity in quantum processor named as 'quprocessor'. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

The article is a short opinionated review of the quantum treatment of electromagnetic circuits, with no pretension to exhaustiveness. This review, which is an updated and modernized version of a previous set of Les Houches School lecture notes, has three main parts. The first part describes how to construct a Hamiltonian for a general circuit, which can include dissipative elements. The second part describes the quantization of the circuit, with an emphasis on the quantum treatment of dissipation. The final part focuses on the Josephson nonlinear element and the main linear building blocks from which superconducting circuits are assembled. It also includes a brief review of the main types of superconducting artificial atoms, elementary multi-level quantum systems made from basic circuit elements. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Energy efficiency has become the primary parameter for the design of next-generation single flux quantum (SFQ) circuits. This, however, needs to be balanced with optimization for clock speed and bias margins. Here, we experimentally study the tradeoff between circuit activity, energy efficiency, and bias margins for zero static power dissipation ERSFQ circuits. For ERSFQ, dc power is provided by a Josephson transmission line (JTL) called a “feeding” JTL (FJTL), which acts as a voltage source. As a test case, shift registers and multiplexers were laid out and fabricated in both HYPRES's and MIT-LL's 10-kA/cm2 fabrication processes and tested at low (∼kHz) and high (∼GHz) clock frequencies. The functional bias margins for these circuits increase significantly from +/–4% to over +/–19% when the Josephson junction count in the FJTL was increased to ∼30% of total dc bias current of the circuit. Based on our findings, we discuss how to optimize ERSFQ circuits for both energy efficiency and dc bias margins. [ABSTRACT FROM PUBLISHER]

Superconductor-based adiabatic quantum-flux-parametron (AQFP) logic holds tremendous promise toward building extremely energy efficient computing systems with bit energies approaching 100  k_B \textT. The majority logic gate is the basis for how all AQFP logic gates are created. By reconsidering the logic design approach of digital circuits using majority logic instead of conventional AND/OR/NOT logic, circuits can potentially use fewer gates overall. This may lead to lower circuit complexities in terms of Josephson junctions, and in turn lower power consumption as well as lower latencies. As a first step toward exploiting majority logic in AQFP technology, we explore how majority-logic-optimized designs of the Kogge–Stone and Brent–Kung adder architectures scale in terms of complexity, latency, area, and energy/operation as we increase the data word size from 8 to 64 bit. Next, we implement 8-bit prototypes of both adders for experimental demonstration. The designs have been fabricated using the 2.5 kA/ \textcm^2 AIST standard process 2 and have demonstrated successful operation in low-frequency testing. Both adders consist of $\sim$1000 Josephson junctions and are designed for 5 GHz operation with a five-cycle latency. [ABSTRACT FROM PUBLISHER]

Once focused solely on computation speed, superconducting computing is now proving useful in hybrid systems where its unique capabilities complement conventional computing technologies. Energy efficiency has become a strong motivation for developing large-scale superconducting systems. [ABSTRACT FROM AUTHOR]

Interfacing superconducting rapid single flux quantum logic with room temperature electronics requires the development of low-power semiconductor circuitry capable of operating at tens of Gb/s while maintaining sufficient signal to noise to achieve acceptable bit-error-rates. Such data-links must operate with sufficiently low power consumption to permit tens to hundreds of parallel channels to coexist in a single cryostat. This requires a careful trade-off between the power and noise performance of the cryogenically cooled digital amplifiers. Previously demonstrated ultra low-power cryogenic-to-room temperature digital data links have been limited to data rates on the order of a few Gb/s. In this paper we demonstrate a temperature distributed amplifier chain optimized for 30 Gb/s data transmission and consuming just 140 microwatts at 4 K. [ABSTRACT FROM PUBLISHER]

New superconductor single flux quantum logics with no static power dissipation in bias resistors, such as Reciprocal Quantum Logic (RQL), offer opportunities to create energy-efficient superconductor processors operating at high frequencies with ultra-low power consumption. This paper discusses the results of our work on the cell-level design and analysis of a benchmark set of 32-/64-bit RQL processor integer and floating-point units such as adders, multipliers, an arithmetic-logic unit, and an array shifter, as well as small 1–4 Kbit RQL on-chip storage components such as register files, on-chip memory, and the top level caches. Our layout-aware design process includes the complete cell-level design and approximate physical layout of the circuits followed by the VHDL simulation, verification, and energy profiling using our RQL VHDL cell library tuned to the future MIT Lincoln Laboratory 10 \kA/cm^2 248 nm process with 10 Nb metal layers and the minimum JJ critical current of 38 \mu\A. Our designs have the energy efficiency of $\sim$1.0 single-precision TFLOPS/W and $\sim$0.5 double-precision TFLOPS/W for floating-point units, and $\sim$1–24 TOPS/W for 32-bit integer units at room temperature using the cryocooling efficiency of 0.1 $\%$ (1000 W/W). The 1–4 Kbit 32-/64-bit multi-ported scratchpad memory, register files, write-through and write-back caches designed with RQL Non-Destructive Read-Out storage cells have the average energy consumption of 3.0–9.5 fJ/bit/operation at room temperature using the cryocooling efficiency of 0.1 $\%$. While these results are very promising, more work is needed to evaluate the contribution of the energy costs of instruction scheduling and off-chip main memory access to the energy efficiency of RQL computing across a whole system. [ABSTRACT FROM PUBLISHER]

We use a combination of global back-gating and local top-gating to define nanoscale devices in the two-dimensional electron gas at the LaAlO3-SrTiO3 interface, demonstrating an efficient way for much finer spatial control over the properties of the interface, as compared to back-gating alone. The devices show indications of an inhomogenous superconducting weak link. The variation of critical current with perpendicular magnetic field shows evidence of oscillations, which hints at Josephson coupling. The variation of the critical current and zero bias resistance with temperature is consistent with short, overdamped weak links. We show that the applied top-gate voltage provides a strong handle on the properties of these weak links. This technique can be an important tool to define a variety of device structures in this system, allowing us to probe the nature of superconductivity in the LaAlO3-SrTiO3 interface system in different ways. [ABSTRACT FROM AUTHOR]

We use a combination of global back-gating and local top-gating to define nanoscale devices in the two-dimensional electron gas at the LaAlO3-SrTiO3 interface, demonstrating an efficient way for much finer spatial control over the properties of the interface, as compared to back-gating alone. The devices show indications of an inhomogenous superconducting weak link. The variation of critical current with perpendicular magnetic field shows evidence of oscillations, which hints at Josephson coupling. The variation of the critical current and zero bias resistance with temperature is consistent with short, overdamped weak links. We show that the applied top-gate voltage provides a strong handle on the properties of these weak links. This technique can be an important tool to define a variety of device structures in this system, allowing us to probe the nature of superconductivity in the LaAlO3-SrTiO3 interface system in different ways. [ABSTRACT FROM AUTHOR]

At present, superconducting integrated circuit layouts are verified through a variety of techniques. A layout-versus-schematic method implemented in Cadence allows extraction of circuit schematics with certain geometry-dependent parameters. Lmeter calculates inductance in a layout network and, with proper setup, may also calculate resistance separately. Recently, InductEx was introduced to calculate multiterminal network inductance in a superconductor structure with support for more complicated 3-D geometries. Here, we present an improvement to InductEx that allows resistance, inductance, and Josephson junction critical current extraction of a full superconducting digital logic gate or cell in a single execution, as well as in reasonable time. We show how InductEx was designed to operate on tape-out ready layouts and, through example, how it is used for full-gate layout verification of contemporary logic cells. [ABSTRACT FROM PUBLISHER]

A new YBCO superconducting linear propulsion system that uses the Meissner effect for thrust is proposed. A YBCO bulk is used in the vehicle, which is excited synchronous with a magnetic field traveling wave. The propulsion system's model is developed using a magnetic circuit method and the Maxwell stress tensor analysis. The vehicle acceleration and thrust force characteristics previewed from that model are verified and analyzed by practical measurements and a set of essays using the prototype built in our laboratory. Major errors came for thermally activated flux creep and current conduction in the YBCO during its passage through the excitation system. The total magnetic field at the superconductor's surface decreases, reducing thrust force. Despite these secondary effects, achieved results show the potential of this new approach for future electric propulsion systems. [ABSTRACT FROM PUBLISHER]

Quantum phase‐slips, which are the exact duals of Josephson junctions (JJs), are promising for several applications in classical and quantum superconducting electronic circuits. The experimental testing of the phase‐slip phenomena and identifying these applications has been challenging. In this reported work, the use of a dual to a JJ model to implement a SPICE model of a quantum phase‐slip junction (QPSJ) in JSPICE3, in order to explore possible circuit applications, is demonstrated. A transient analysis model of the device is presented and an example of an I–V curve simulation of the device, along with a simulation of a possible circuit application of the device, are also shown. [ABSTRACT FROM AUTHOR]

Using the superconducting properties of Josephson junctions enable extremely high switching speeds unmatched in semiconducting electronics. Much research has been conducted in recent decades in order to produce high performance electronics based on Josephson junction logic. In addition to the high speeds attainable by this technology, also of significance is the very low heat dissipated by Josephson circuits. Josephson devices have made great strides in the last ten years with microprocessors reaching levels of integration as high as 105 junctions/cm2. Dissipation in these devices is easily managed, but integrations reaching 107 must be considered if Josephson electronics are to compete with the complexity and functionality of semiconducting electronics. Coupling this level of integration with dissipations of 0.34 and 2.98 μW/junction in low and high temperature cases respectively, produces large heat fluxes difficult to remove at cryogenic temperatures. While other technical difficulties currently overshadow heat transfer concerns, the future of Josephson electronics research will likely need to address them [ABSTRACT FROM PUBLISHER]

High temperature superconductors (HTS) promise to achieve electrical performance superior to that of conventional electronics. For application in space systems, HTS systems must simultaneously achieve lower power, weight, and volume than conventional electronics, and meet stringent space qualification and reliability requirements. Most effort to date has focused on passive RF/microwave applications. However, incorporation of active microwave components such as amplifiers, mixers, and phase shifters, and on-board high data rate digital signal processing is limited by the power and weight of their spacecraft electronic and support modules. Absence of data on active HTS components will prevent their utilization in space. To validate the feasibility in space of HTS circuits and components based on Josephson junctions, we need to demonstrate HTS circuits and critical supporting technologies, such as space-qualified packaging and interconnects, closed-cycle cryocooling, and interface electronics. This paper describes the packaging, performance, and space test plan of an integrated, space-qualified experimental package consisting of HTS Josephson junction circuits and all the supporting components for NRL's high temperature superconductor space experiment (HTSSE-II). Most of the technical challenges and approaches are equally applicable to passive and active RF/microwave and digital electronic components, and this experiment will provide valuable validation data. [ABSTRACT FROM AUTHOR]

We have developed a process for fabrication of HTS single-flux-quantum logic circuits based on edge SNS junctions which requires six epitaxial film layers and six mask levels. The process was successfully applied to fabrication of small-scale circuits (/spl les/10 junctions). This paper examines the materials properties affecting the reproducibility of YBCO-based SNS junctions, the low inductance provided by an integrated YBCO ground plane, and electrical isolation by SrTiO/sub 3/, or Sr/sub 2/AlTaO/sub 6/, ground-plane and junction insulator layers. Some of the critical processing parameters identified by electrical measurements, TEM, SEM, and AFM were control of second-phase precipitates in YBCO, oxygen diffusion, Ar ion-milling parameters, and preparation of surfaces for subsequent high-temperature depositions. [ABSTRACT FROM PUBLISHER]

A flux shuttle shift register with master and slave sections is implemented with YBCO Josephson junctions along only one straight grain boundary of a bicrystal substrate. The investigated prototype comprises a write circuit, four master/slave shift register cells and a dynamic read out circuit for single flux quanta. The simulation results and the layout are presented. [ABSTRACT FROM PUBLISHER]