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This paper proposes a design methodology for a synthesizable, fully digital TDC architecture. The TDC was implemented using a hardware description language (HDL), which improves portability between platforms and technologies and significantly reduces design time. The proposed design flow is fully automated using TCL scripting and standard CAD tools configuration files. The TDC is based on a Tapped Delay Line architecture and explores the use of Structured Data Path (SDP) as a way to improve the TDL linearity by homogenizing the routing and parasitic capacitances across the multiple TDL's steps. The studied approach also secures a stable, temperature independent measurement operation. The proposed TDC architecture was fabricated using TSMC 180nm CMOS process technology, with a 50MHz reference clock and a supply voltage of 1.8V. The fabricated TDC achieved an 111ps RMS resolution and a single-shot precision of 54ps (0.48 LSB) and 279ps (2.51 LSB), with and without post-measurement software calibration, respectively. The DNL across the channel is mostly under 0.3 LSB and a maximum of 8 LSB peak-to-peak INL was achieved, when no calibration is applied.

Summary: This work presents a comprehensive literature review on different topologies of time‐to‐digital converters (TDCs). A brief history, applications, classification, characterization, and working principle of each TDC are mentioned. A survey of both Field Programmable Gate Array (FPGA) and Application‐Specific Integrated Circuit (ASIC) architectures is covered. The trade‐off with respect to applications, pros, and cons of different architectures and future scope of TDC as an alternative data converter is also explored. [ABSTRACT FROM AUTHOR]

This article presents a low-power, all-digital multichannel time-to-digital converter (TDC) for light detection and ranging (LiDAR) sensors. The proposed TDC architecture measures the time interval through a coarse counter, middle, and fine delay line-based interpolation technique (the Nutt method). Automatic calibration by middle and fine all-digital delay-locked loops (ADDLLs) is provided to ensure the stability of the generated time slots. Charge pump, loop filter, and voltage-controlled delay line inside the conventional analog delay-locked loops (DLLs) are replaced by an accumulator (ACC) and digitally controlled delay line (DCDL). This makes the design particularly compact, low power, and suitable for multichannel applications. The presented architecture can generate information for amplitude variation (walk error) compensation. This information is generated by measuring the pulsewidth and position of three successive STOP pulses inside each channel within a single-shot measurement. A low-jitter injection-locked frequency multiplier (ILFM) generates a 625-MHz internal clock signal out of 25-MHz external reference oscillator, which shrinks the number of delay elements to cover one period of the reference clock and improves the precision of the TDC. Operation at higher frequency provides high throughput and short conversion time (less than 3 ns). The three-level TDC offers 13.1- $\mu \text{s}$ maximum input range and 50-ps resolution. The measured DNL and INL of the TDC circuit are 0.47 and 0.71 LSB, respectively. The TDC circuit is implemented in a 180-nm standard CMOS process with a die size of 1.5 mm $\times1.5$ mm. The total power consumption of the multichannel TDC is 87.6 mW. [ABSTRACT FROM AUTHOR]

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A time-to-digital converter (TDC) often consists of sophisticated, multilevel, subgate delay structures, when time intervals need to be measured precisely. The resolution improvement is rewarding until integral nonlinearity (INL) and random jitter begins to limit the measurement performance. INL can then be minimized with calibration techniques and result postprocessing. The TDC architecture based on a counter and timing signal interpolation (the Nutt method) makes it possible to measure long time intervals precisely. It also offers an effective means of improving precision by averaging. Traditional averaging, however, demands several successive measurements, which increases the measurement time and power consumption. It is shown here that by using several interpolators that are sampled homogeneously over the clock period, the effects of limited resolution, interpolation nonlinearities, and random noise can be markedly reduced. The designed CMOS TDC utilizing internal systematic sampling technique achieves 3.0-ps root mean square (RMS) single-shot precision without any additional calibration or nonlinearity correction. [ABSTRACT FROM AUTHOR]

The paper describes a new method for high resolution nuclear timing spectroscopy system using tracking ADCs and free running ramp to give the timing resolution of few ps over wide dynamic range of time interval extending up to few µs. The method makes use of tracking ADCs with 16 bit resolution with low conversion time of nearly 1 µs along with a free running ramp which is given as input to the two ADCs. Both the ADCs and ramp are designed to track their characteristics in order to neutralize the errors due to drift in their characteristics and hence complex system of spectrum stabilization is not required. ADC1 digitizes ramp input at the arrival of START pulse and ADC2 digitizes ramp input at the arrival of STOP pulse. The difference between digital codes of these ADCs is a measure of time interval between START and STOP pulses. New system doesn't require delay and hence biased amplifier. System has dead time of 1 µs and spectrum stabilization is easy. [ABSTRACT FROM AUTHOR]

Most systems used in quantum physics experiments require the efficient and simultaneous recording different multi-photon coincidence detection events. In such experiments, the single-photon gated counting systems can be applicable. The main sources of errors in these systems are both instability of the clock source and their imperfect synchronization with the excitation source. Below, we propose a solution for improvement of the metrological parameters of such measuring systems. Thus, we designed a novel integrated circuit dedicated to registration of signals from a photon number resolving detectors including a phase synchronizer module. This paper presents the architecture of a high-resolution (~60 ps) digital phase synchronizer module cooperating with a multi-channel coincidence counter. The main characteristic feature of the presented system is its ability to fast synchronization (requiring only one clock period) with the measuring process. Therefore, it is designed to work with various excitation sources of a very wide frequency range. Implementation of the phase synchronizer module in an FPGA device enabled to reduce the synchronization error value from 2.857 ns to 214.8 ps.

A new time-to-digital converter (TDC) with high resolution and high precision is designed and tested in this paper. The converter is realized by combining coarse clock counter with a two-stage delay-line loop shrinking interpolator (DLLSI) based on Vernier configuration, and its prototype has been implemented in a low-cost flash field-programmable gate array device SmartFusion A2F200M3F (Actel). Delay-line loops are used to achieve differential Vernier delay unit and directly shrink the time interval. In order to improve the resolution, decrease measurement time, and diminish the jitter of the cyclic pulse, a two-stage DLLSI method is proposed. The first-stage interpolator rapidly shrinks the measured time interval with low resolution, and the second-stage interpolator determines the final fine resolution. The resolutions are dependent on the entire delay time differences between two delay-line loops of each interpolator. The optimal resolutions are theoretically calculated, and statistic code density test is used to estimate the resolution of the implemented TDC. The implemented two-stage DLLSI has achieved 8.5-ps resolution with 42.4-ps standard deviation and 10-ns dynamic range. The maximum integral and differential nonlinearity errors are less than 7.8 and 3.1 ps. [ABSTRACT FROM AUTHOR]

• This article reports recent developments in time-to-digital conversion (TDC) techniques. • A comprehensive picture of major trends and advancements of the TDC design is presented. • The architectures, implementations and performance of TDCs including time resolution, conversion range, conversion time, power consumption, and converter nonlinearities are discussed in details. Time-to-digital converters (TDCs) are key components of time-mode circuits and enablers for digital processing of analog signals encoded in time. Since design of time-mode circuits facilitates replacing analog blocks with digital circuitry, TDCs pave the way to hardware-efficient and purely digital architectures in deep-submicron semiconductor technology. The design and implementation of modern TDCs is heterogeneous, shaped in multiple directions, and driven by CMOS process downscaling along with application demands. The substantial research effort is made in more intensive digital implementations, optimization of techniques for high resolution, increasing input range and linearity, reduced conversion time, power consumption and silicon area. The calibration and mismatch-tolerant, as well as anti-PVT-variation and anti-metastability design techniques are of growing importance in order to alleviate imperfections of nanoscale CMOS technologies. The paper surveys recent developments of time-to-digital conversion techniques to give a possibly comprehensive picture of major trends and design advancements. Finally, we highlight TDC design challenges for cutting-edge applications such as All-Digital Phase Locked Loops for high data rate wirelesss communication systems operating in the millimeter-wave band. [ABSTRACT FROM AUTHOR]

An embedded time interval data acquisition system (DAS) is developed for zero power reactor (ZPR) noise experiments. The system is capable of measuring the correlation or probability distribution of a random process. The design is totally implemented on a single Field Programmable Gate Array (FPGA). The architecture is tested on different FPGA platforms with different speed grades and hardware resources. Generic experimental values for time resolution and inter-event dead time of the system are 2.22 ns and 6.67 ns respectively. The DAS can record around 48-bit x 790 kS/s utilizing its built-in fast memory. The system can measure very long time intervals due to its 48-bit timing structure design. As the architecture can work on a typical FPGA, this is a low cost experimental tool and needs little time to be established. In addition, revisions are easily possible through its reprogramming capability. The performance of the system is checked and verified experimentally.

The paper is focused on design of time-to-digital converters based on successive approximation (SA-TDCs—Successive Approximation TDCs) using binary-scaled delay lines in the feedforward architecture. The aim of the paper is to provide a tutorial on successive approximation TDCs (SA-TDCs) on the one hand, and to make the contribution to optimization of SA-TDC design on the other. The proposed design optimization consists essentially in reduction of circuit complexity and die area, as well as in improving converter performance. The main paper contribution is the concept of reducing SA-TDC complexity by removing one of two sets of delay lines in the feedforward architecture at the price of simple output decoding. For 12 bits of resolution, the complexity reduction is close to 50%. Furthermore, the paper presents the implementation of 8-bit SA-TDC in 180 nm CMOS technology with a quantization step 25 ps obtained by asymmetrical design of pair of inverters and symmetrized multiplexer control.

This brief introduces a successive approximation time-to-digital converter based on a novel algorithm denoted as successive approximation register with continuous disassembly (SAR-CD). The main advantage of the proposed SAR-CD algorithm is that it moves the conditioning between the evaluated bits to the digital domain, after all the bits are evaluated. Simulation results show promising enhancements in power consumption compared with the state-of-the-art designs. A full 10-bit architecture is introduced using 65-nm CMOS technology as a case study with simulation power consumption of 2.8 mW at a sampling rate of 29.4 Msample/s from 1-V power supply with an effective number of bits value of 8.63 bits and a maximum differential nonlinearity of 1 least significant bit. [ABSTRACT FROM PUBLISHER]

Remote Raman spectroscopy is widely used to detect minerals, explosives and air pollution, for example. One of its main problems, however, is background radiation that is caused by ambient light and sample fluorescence. We present here, to the best of our knowledge, the first time a distance-resolving Raman radar device that is based on an adjustable, time-correlated complementary metal-oxide-semiconductor (CMOS) single-photon avalanche diode line sensor which can measure the location of the target sample simultaneously with the normal stand-off spectrometer operation and suppress the background radiation dramatically by means of sub-nanosecond time gating. A distance resolution of 3.75 cm could be verified simultaneously during normal spectrometer operation and Raman spectra of titanium dioxide were distinguished by this system at distances of 250 cm and 100 cm with illumination intensities of the background of 250 lux and 7600 lux, respectively. In addition, the major Raman peaks of olive oil, which has a fluorescence-to-Raman signal ratio of 33 and a fluorescence lifetime of 2.5 ns, were distinguished at a distance of 30 cm with a 250 lux background illumination intensity. We believe that this kind of time-correlated CMOS single-photon avalanche diode sensor could pave the way for new compact distance-resolving Raman radars for application where distance information within a range of several metres is needed at the same time as a Raman spectrum.

Asynchronous time measurement systems, such as tapped delay lines and BOUNCE, consist of a rather large number of independently operating elements, which all have to be calibrated in a rather tedious, preliminary setup process. The required calibration time grows linearly in the number of instantiated elements, which can be as large as thousands of elements in practically relevant systems. Recent research has suggested to seamlessly integrate a second time measurement system, known as X-ORCA, to make the required calibration time constant, i.e., independent of the number of elements. Even though X-ORCA is operating asynchronously as well, it is able to determine the phase shifts between two signals at various on-board locations simultaneously . This paper integrates X-ORCA to calibrate BOUNCE. This hybrid calibration approach improves BOUNCE’s precision from 170 ps to 30 ps. This paper describes this approach in detail, and provides the results of intensive tests, which include different FPGAs, temperature changes, and validation by means of external laboratory equipment. [ABSTRACT FROM AUTHOR]

Time interval (TI) is one of the basic quantities. Its measurement is not included only in the activities running in the time and frequency metrology but also included in the measurement of many other quantities that depend on time interval measurement (TIM). This means that improving the accuracy and reducing the measurement uncertainty of TI will reflect also on improving the accuracy and reducing the measurement uncertainty of many other quantities. To do that, we need to decrease or eliminate the effect of the dominant factors that degrade the quality of TIM. One of the major contributors to the measurement uncertainty of TI is the internal error of the time interval counter (TIC) used in the measurement. In this paper we introduce a methodology with which we can estimate precisely the internal error of the counter and eliminate its effect. [ABSTRACT FROM AUTHOR]

The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns. [ABSTRACT FROM AUTHOR]

Monitoring the performance of the primary frequency sources continuously through comparing it versus the transfer standards and the calibration of the secondary frequency sources periodically versus the primary ones are of the main missions assigned to any time and frequency laboratory either it was a calibration laboratory or a national metrological laboratory. An automatic Generalized System (GS) for monitoring/calibrating any frequency source that has a Relative Frequency Offset (RFO) greater than 1×10-14Hz/Hz has been built. This GS is able to use either of two measurement methods according to the accuracy of the frequency source being measured. A graphical programming language, which is Labview, was used in writing the software required for both hardware control and data logging. So, the software can be easily reconfigured for any upgrading plans. Also a flexible arrangement for the hardware setup was used such that two measurement systems are merged in one system. So, according to the user needs the right hardware setup can be chosen. The results obtained by this GS were verified through comparing them to those generated by one of the commercial turnkey solutions. [ABSTRACT FROM AUTHOR]

Measuring the time interval (TI) with an accuracy in the picoseconds range requires having an accurate measurement system and minimizing the sources of errors contributed by the signal being measured. Trigger level timing error is one of the main sources of error that dramatically affects the measurement accuracy. In this article we study the effect of changing the trigger level on the TI measurement accuracy for sinusoidal signals, introduce a laboratory method for determining the optimum trigger level that leads to the highest measurement accuracy, and make a method validation. [ABSTRACT FROM AUTHOR]

At April 2003 there were 25 National Metrology Institutes in 25 countries that are members in the European Association of National Metrology Institutes (EURAMETs) agreed to participate in an inter-laboratory comparison for time interval measurement (TIM). The main target of this comparison, as mentioned by EURAMET, was to support the current calibration measurement capabilities for TI and to gain better understanding of the TIM. Cable delay measurement was taken as an example. The time delay of three different length coaxial cables (short, medium, and long) was measured. The majority of the laboratories used the Counter Method. There was a large span between the measurements for all cables (about 1 ns). Consequently, the measurement results that had been published at 2007 were not satisfied for the participant laboratories. In this article, we study the probable reasons for this considerable span between the different measurements for the same artifact. [ABSTRACT FROM AUTHOR]

A picosecond resolution time-to-digital converter (TDC) is presented. The resolution of a conventional delay chain TDC is limited by the delay of a logic buffer. Various types of recent TDCs are successful in breaking this limitation, but they require a significant calibration effort to achieve picosecond resolution with a sufficient linear range. To address these issues, we propose a simple method to break the resolution limitation without any calibration: a Gm \-C integrator followed by a successive approximation register analog-to-digital converter (SAR-ADC). This translates the time interval into charge, and then the charge is quantized. A prototype chip was fabricated in 90 nm CMOS. The measurement results reveal a 1 ps resolution, a -0.6/0.7 LSB differential nonlinearity (DNL), a -1.1/2.3 LSB integral nonlinearity (INL), and a 9-bit range. The measured 11.74 ps single-shot precision is caused by the noise of the integrator. We analyze the noise of the integrator and propose an improved front-end circuit to reduce this noise. The proposal is verified by simulations showing the maximum single-shot precision is less than 1 ps. The proposed front-end circuit can also diminish the mismatch effects. [ABSTRACT FROM PUBLISHER]

A multichannel time-to-digital converter (TDC) implemented with 0.35-\mu \m complementary metal–oxide–semiconductor technology that uses a low-frequency crystal as reference and measures the time intervals with counter and delay line interpolation techniques is described. The multichannel measurement architecture provides information on the time intervals between several timing signals. The circuit can be used for laser time-of-flight distance measurements, e.g., where it can determine time intervals between a transmitted laser pulse and several reflected pulses and also pulsewidths or rise times, to compensate for the timing walk error. This paper shows how several measurement channels can be integrated into one TDC without losing the measurement performance. The circuit offers a measurement precision that is better than 8 ps and a measurement range of up to 74 \mu\s. In terms of laser distance measurement, its performance is equivalent to millimeter-level precision within an 11-km range. [ABSTRACT FROM PUBLISHER]

To date, research on the motor control of hand function in cerebral palsy has focused on children with hemiplegia, although many persons with diplegic cerebral palsy (dCP) have asymmetrically decreased hand function. We explored the predictive capabilities of the motor system in a simple motor task of lifting a series of virtual objects for five persons with spastic dCP and five age-matched controls. When a person lifts an object, s/he uses an expectation of the weight of the object to generate a motor command. We asked the study subjects to lift a series of increasing weights and determined whether they extrapolated from past experience to predict the next weight in the series, even though that weight had never been experienced. Planning of precision grasp was assessed by measurement of the grip force at the beginning of the lifting task and by estimating the motor command. Execution of precision grasp was assessed by measurement of the time interval between the onset of grip and the onset of movement. We found that persons with dCP demonstrated a lack of predictive feed-forward control in their lifting movements: they exhibited a significantly longer time between onset of grip and onset of movement than the control subjects and they did not predict the weight of the next object in the lifting task. In addition, for subjects with dCP, the time between the onset of grip and the onset of movement of the dominant hand correlated strongly with the outcome of a hand function test. We postulate that a higher-order motor planning deficit in addition to execution deficit are evident in the subjects with spastic diplegic. [ABSTRACT FROM AUTHOR]

A high-resolution time-to-digital converter (TDC) was designed and tested. The converter is based on the fundamental method of counting the full clock cycles of a low-phase-noise reference clock and using a single-stage interpolating method employing time-to-amplitude converters that are based on Miller integrators. Counters and other control logic were implemented on a field-programmable gate array, and the interpolation units were constructed using discrete components. The single-shot precision of the uncompensated converter is about 1.8 ps over a time interval range of 0 to 328 \mu\s. Single-shot precision is limited by the nonlinearities of the interpolators. These measurement errors caused by the nonlinearities are systematic, and thus, precision can be improved to 1 ps by a simple integral nonlinearity compensation. Other important factors that contribute to single-shot precision are the N-cycle jitter of the reference clock and the noise generated by the TDC circuit itself. By careful design, these errors can be made small enough to achieve picosecond-level precision. [ABSTRACT FROM AUTHOR]

An integrated receiver channel for a pulsed time-of-flight (TOF) laser rangefinder has been designed and fabricated in a 0.35-\mu\m SiGe BiCMOS process. The receiver channel generates a timing mark for the TDC by means of a leading-edge timing discriminator that detects the crossover of the received pulse with respect to a set reference level. The walk error generated by the amplitude variation is compensated in the time domain on the basis of the measured dependence of the walk on the length of the received pulse. The measurement accuracy is \pm15 ps with compensation within a dynamic range of 1:100 000, and the single-shot precision and power consumption are 120 ps for a minimum detectable signal of \sim\!1\ \mu\A and 115 mW, respectively. [ABSTRACT FROM AUTHOR]

This paper analyzes the process from gestation to maturity of fast electronics, describes the three-level relations formed in the development of fast electronics, i.e. that of application, technique and theory, and summarizes in brief the progresses in simulation of electromagnetic fields, high-speed parallel sampling, and research of time jitter. Application results of fast electronics in national economy and national major science projects are also introduced. [ABSTRACT FROM AUTHOR]

This paper describes a time-to-digital converter (TDC) with ~1.2 ps resolution and ~327 μs dynamic range suitable for laser range-finding application for example. The resolution of ~1.2 ps is achieved with interpolation based on a cyclic time domain successive approximation (CTDSA) method that resolves the time difference between two non-repetitive signals using binary search. The method utilizes a pair of digital-to-time converters (DTC), the propagation delay difference between which is implemented by digitally controlling the unit load capacitors of their delay cells, thus enabling sub-gate delay timing resolution. The rms single-shot precision, i.e., standard deviation σ-value of the TDC is 3.2 ps, which is achieved by using an external integral nonlinearity look-up table (INL-LUT) for the interpolators. The power consumption is 33 mW at 100 MHz with a 3.3 V operating voltage. The prototypes were fabricated in a 0.35 μm CMOS process. [ABSTRACT FROM AUTHOR]

A new architecture for the on-chip measurement of short-time intervals is proposed in this paper. The measurement method is similar to a typical low-voltage measurement setup where the input signals are first amplified and then measured to relax the dynamic range of the succeeding analog-to-digital converter. In the proposed method, narrow time intervals are first amplified by a time amplifier (TAMP) and then measured by a time-to-digital converter. A delay-locked-loop (DLL) circuit is utilized to design a feedback time amplifier in which the gain is readily programmed by input data to any integer value within a range specified by the number of delay cells in the DLL. The TAMP's gain remains rather unchanged under process and temperature variations due to the inherent negative feedback of the DLL system. The circuit is implemented using complementary metal-oxide semiconductor (CMOS) 0.18-μm technology occupying less than 0.63 mm² of the silicon area. The simulation results show that the proposed scheme can successfully be employed to measure time intervals in the range of a few tens of picoseconds with acceptable accuracy. [ABSTRACT FROM AUTHOR]

A fully integrated time-to-digital converter (TDC) for a pulsed time-of-flight laser rangefinder has been designed and fabricated by a standard 0.18-μm CMOS process. The time-to-digital conversion is realized by counting the full clock cycles of an on-chip ring oscillator between timing signals and by recording the state of its 12 phases at the moment of arrival of the timing signals and their delayed replicas. The frequency of the oscillator is stabilized to an on-chip voltage reference by means of a frequency-to-voltage-converter-based feedback loop. The resolution and single-shot precision (standard deviation) of the TDC are ~60 ps and less than ~50 ps, respectively, in a range of 80 ns. The worst-case temperature dependence of the TDC is less than 50 ppm/°C in the temperature range of 0 °C to 70 °C, corresponding to 0.6 mm/°C at a distance of 12 m (80 ns). The power consumption of the TDC is less than 18 mW. [ABSTRACT FROM AUTHOR]

An integrated receiver that includes both the time-to-digital converter (TDC) and the receiver channel and is intended for a pulsed time-of-flight laser rangefinder with a measurement range of approximately 10 m has been designed and fabricated in a standard 0.13 μm CMOS process. The receiver operates by detecting the current pulse of an optical detector and producing a stop timing mark for the TDC by means of a leading edge timing discriminator. The TDC is used to measure the actual time interval between the start and stop pulses and the slew-rate of the stop pulse, to compensate for a walk error produced in the discriminator. The single-shot precision of the whole receiver is 250 ps for a minimum detectable signal, and its accuracy and power consumption are ±37 PS with compensation within a dynamic range of at least 1:10,000 and less than 45 mW, respectively. The size of the die is 1300 μm x 1300 μm including pads. [ABSTRACT FROM AUTHOR]

Abstract: Purpose: The purpose of this study was to compare judgments of stuttering made by students and clinicians with previously available judgments made by highly experienced judges in stuttering. Method: On two occasions, 41 university students and 31 speech-language pathologists judged the presence or absence of stuttering in each of 216 audiovisually recorded 5-s intervals of the speech of adults who stutter. Intrajudge and interjudge agreement were calculated, and comparisons were made to judgments previously made about the same recordings by 10 highly experienced judges of stuttering. Results: Students and clinicians showed similar and relatively high levels of intrajudge and interjudge agreement, but both students and clinicians identified less than half as much stuttering as the highly experienced judges had identified. Conclusions: These results replicate previous findings of high agreement coexisting with low accuracy in students’ judgments of stuttering, extending those findings to show that similar problems are evident in judgments made by practicing clinicians. Implications include the need for explicit stuttering judgment training programs for both students and practicing clinicians. Educational objectives : After reading this article, the reader will be able to: (1) describe different methods for identifying stuttering and possible problems associated with each method; (2) describe two different methods for reporting interjudge reliability; (3) describe how the identification of stuttering differs for student, clinician, and highly experienced judges. [Copyright &y& Elsevier]

A high-precision CMOS time-to-digital converter IC has been designed. Time interval measurement is based on a counter and two-level interpolation realized with stabilized delay lines. Reference recycling in the delay line improves the integral nonlinearity of the interpolator and enables the use of a low frequency reference clock. Multi-level interpolation reduces the number of delay elements and registers and lowers the power consumption. The load capacitor scaled parallel structure in the delay line permits very high resolution. An INL look-up table reduces the effect of the remaining nonlinearity. The digitizer measures time intervals from 0 to 204 μs with 8.1 ps rms single-shot precision. The resolution of 12.2 μs from a 5-MHz external reference clock is divided by means of only 20 delay elements. [ABSTRACT FROM AUTHOR]

An integrated digital CMOS time-to-digital converter with sub-gate delay LSB width and 50 ps single-shot precision σ-value has been designed and implemented for a laser range-finding application. The measurement is based on a counter and a novel two-step parallel interpolation that uses only 32 delay elements to provide 128 LSBs in the interpolator within the reference clock cycle. The circuit was fabricated in the AMS 0.8 μm CMOS process and the current consumption of the circuit is <20 mA from a single +5 V supply. [ABSTRACT FROM AUTHOR]