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Summary: A single‐source switched capacitor multilevel inverter (SCMLI) topology utilizing only 10 switches and 1 diode with the capability of generating seven output voltage levels and a triple voltage boosting factor is proposed in this paper. The converter has capacitors that are self‐balanced and do not require any additional circuitry. The multicarrier sinusoidal pulse width modulation (PWM) technique is used to generate various switching signals for the 10 switches. Moreover, the reliability analysis using the Markov model has been carried out to assess the lifespan of power electronic components used in the proposed converter. The converter's performance is analyzed when an open circuit fault occurs in one or multiple switches. Power loss and efficiency in the converter are calculated by PLECS software using thermal modeling. The efficiency of SCMLI was found to be 97.6% for a 300 W load. The inverter working is verified by building a 500 W prototype in the lab. The experimental results in steady‐state and dynamic conditions agree with the theoretical and simulation analysis. [ABSTRACT FROM AUTHOR]

This paper presents a review of the most common power converters and torque ripple minimisation approaches for switched reluctance motors (SRMs). Unlike conventional three-phase AC motors, namely squirrel cage induction motors and permanent magnet synchronous motors, which require a typical three-phase inverter for operation, the switched reluctance motor requires a different topology power converter for reliable and efficient operation. In addition, due to the non-linear, discrete nature of SRM torque production, torque ripple is severely pronounced, which is undesirable in servo applications like electric vehicles. Hence, deploying a proper torque control function for smooth and quiet motor operation is crucial. This paper sheds light over the most popular SRM power converters as well as torque ripple minimisation methods, and it suggests an optimal SRM drive topology for EV applications. [ABSTRACT FROM AUTHOR]

This article describes a 17-level switched-capacitor-based eight-times-boosting gain inverter. The inverter is made up of a DC power source, thirteen switches, three diodes, and three capacitors. The inverter produces seventeen steps during each cycle and crosses the zero line two times in one complete cycle. The proposed inverter has its polarity change mechanism; it is not necessary to use an H-bridge. Three self-balancing capacitors make up this construction. The capacitors automatically balance voltage by connecting in series/parallel to the input voltage source. Logic gates can generate gate pulses with the phase disposition pulse-width modulation technique, which helps to preserve capacitor voltage balance at the same time. The proposed structure was compared to recent papers, analyzing factors including voltage gain, DC sources, semiconductor devices, cost function, and TSV. The proposed configuration offers cost effectiveness and fewer semiconductor devices for providing a 17-level output with sufficient voltage gain. Also, to reduce the capacitor inrush current, soft charging is used. Additionally, the proposed structure's power losses were examined, confirming its efficiency. Finally, an experimental prototype was tested to analyze and validate the suggested structure's performance under various situations. Results show the proposed structure performs well under steady and dynamic situations. [ABSTRACT FROM AUTHOR]

Summary: A new structure of an asymmetrical switched‐capacitor‐based multilevel inverter topology is proposed. The circuit is capable of generating 17‐level boosted output utilizing 11 switches and two DC sources in the ratio of 1:2, having a voltage gain of 2.6 times the input voltage. The boosting capacitors were properly charge‐discharged during one complete cycle without requiring any complex control circuit for voltage balancing. The simulation model of the proposed circuit is developed in MATLAB, and the performance of the circuit is experimentally validated. The thermal modeling using PLECS software for power loss evolution is performed, and the maximum efficiency of 97.70% is achieved by implanting a low switching frequency scheme. The comparison with the other similar topologies shows the proposed topology is better than the other compared topologies in many parameters. The boosted output voltage utilizing reduced components makes the proposed topology feasible for various applications, including solar PV system. [ABSTRACT FROM AUTHOR]

This work introduces an 11-level switched-capacitor multilevel inverter (SCMLI) designed for solar photo-voltaic (PV) applications, capitalizing on the growing popularity of multilevel inverters due to their superior power quality. With a 1.67- times boosting capability, the proposed SCMLI employs 10 switches, 2 DC supplies, and 2 capacitors to achieve an 11-level output voltage waveform. The topology requires only seven driver circuits, incorporating 2 bidirectional switches and 3 complementary pairs of switches. The proposed inverter has intrinsic capacitor self-balancing features since the capacitors are connected across the DC voltage source at different times throughout a basic cycle to charge the capacitors at a level of input voltage. A thorough comparison between the topology and recently developed SCMLI's has been presented. The comparison demonstrates the effectiveness in terms of switches, capacitors, sources, efficiency, total standing voltage (TSV), and boosting capacity. To experimentally validate its performance, the suggested SCMLI undergoes testing using a frequency-based switching method. The topology exhibits low total harmonic distortion (THD) of 7.65% in its output voltage waveform and 0.89% in the output current waveform. [ABSTRACT FROM AUTHOR]

This paper presents a review of the most common power converters and torque ripple minimisation approaches for switched reluctance motors (SRMs). Unlike conventional three-phase AC motors, namely squirrel cage induction motors and permanent magnet synchronous motors, which require a typical three-phase inverter for operation, the switched reluctance motor requires a different topology power converter for reliable and efficient operation. In addition, due to the non-linear, discrete nature of SRM torque production, torque ripple is severely pronounced, which is undesirable in servo applications like electric vehicles. Hence, deploying a proper torque control function for smooth and quiet motor operation is crucial. This paper sheds light over the most popular SRM power converters as well as torque ripple minimisation methods, and it suggests an optimal SRM drive topology for EV applications.

This article describes a 17-level switched-capacitor-based eight-times-boosting gain inverter. The inverter is made up of a DC power source, thirteen switches, three diodes, and three capacitors. The inverter produces seventeen steps during each cycle and crosses the zero line two times in one complete cycle. The proposed inverter has its polarity change mechanism; it is not necessary to use an H-bridge. Three self-balancing capacitors make up this construction. The capacitors automatically balance voltage by connecting in series/parallel to the input voltage source. Logic gates can generate gate pulses with the phase disposition pulse-width modulation technique, which helps to preserve capacitor voltage balance at the same time. The proposed structure was compared to recent papers, analyzing factors including voltage gain, DC sources, semiconductor devices, cost function, and TSV. The proposed configuration offers cost effectiveness and fewer semiconductor devices for providing a 17-level output with sufficient voltage gain. Also, to reduce the capacitor inrush current, soft charging is used. Additionally, the proposed structure’s power losses were examined, confirming its efficiency. Finally, an experimental prototype was tested to analyze and validate the suggested structure’s performance under various situations. Results show the proposed structure performs well under steady and dynamic situations.

This work introduces an 11-level switched-capacitor multilevel inverter (SCMLI) designed for solar photo-voltaic (PV) applications, capitalizing on the growing popularity of multilevel inverters due to their superior power quality. With a 1.67-times boosting capability, the proposed SCMLI employs 10 switches, 2 DC supplies, and 2 capacitors to achieve an 11-level output voltage waveform. The topology requires only seven driver circuits, incorporating 2 bidirectional switches and 3 complementary pairs of switches. The proposed inverter has intrinsic capacitor self-balancing features since the capacitors are connected across the DC voltage source at different times throughout a basic cycle to charge the capacitors at a level of input voltage. A thorough comparison between the topology and recently developed SCMLI’s has been presented. The comparison demonstrates the effectiveness in terms of switches, capacitors, sources, efficiency, total standing voltage (TSV), and boosting capacity. To experimentally validate its performance, the suggested SCMLI undergoes testing using a frequency-based switching method. The topology exhibits low total harmonic distortion (THD) of 7.65% in its output voltage waveform and 0.89% in the output current waveform.

Summary: With an input‐side boost inductor, current source inverter (CSI) naturally has the unique performance of voltage boosting and continuous input current, but its switching devices need to have reverse blocking capability. Switched‐capacitor (SC) multilevel inverter (MLI) features self‐balancing capacitor voltages and flexible structure, but it suffers the problems of inrush charging current of capacitors and pulse input current. By combining the CSI's input characteristics and the SC‐MLI's output features, this work presents a new five‐level inverter. Its input current is continuous, and there is no inrush current. In addition, the voltage gain is improved to 2/(1−d), where d is the duty ratio of the inductor's charging mode. With the unique structure, the duty ratio ranges from 0 to 1, and it is independent of the modulation ratio of the inverter. This makes the control more flexible. In addition to topology, operation, and modulation, parameter design, power loss, and comparison study are analyzed in detail. Finally, simulation results with fuel cell as input, and experimental results are provided to verify the superior performance of the proposed inverter. [ABSTRACT FROM AUTHOR]

Integrating energy sources is essential for having a sustainable energy supply to drive critical loads. Several types of multi-input converters (MICs) can be developed. However, most of them operate with a time-sharing-based scheme, which means that one energy source is utilized at a particular time, and the remaining sources are idle. This control scheme leads to the underutilization of both the converter and input energy sources. In this regard, this paper proposes a configuration of a single switch dual–input single-output (S-DISO) DC-DC converter, which has a simple structure with a reduced number of switches. It can operate without operational constraints on input energy sources or duty ratio utilization. Performance and comparative analysis are presented in different aspects. The effectiveness of the converter performance is validated using hardware experiments. Compared to the theoretical values, a 240 W laboratory prototype hardware circuit is developed and verified.

Summary: A self‐balancing 9‐level inverter is proposed in this paper. To generate a 9‐level voltage with a gain of two requires a single DC source, eight power switches, three capacitors, and two diodes. Without additional circuitry, the voltages of the capacitors in the proposed topology can achieve inherent balance. The peak‐inverse‐voltage (PIV) of six power switches equals or less than the source voltage, and the other two are twice. As power switches are complementary, the proposed topology requires fewer gate drivers. Furthermore, the self‐balancing capability of capacitors' voltage helps in simple control complexity. The description of topology, mode of operation, modulation strategy, and design of the capacitor of proposed topology are presented. The advantages of the proposed inverter are examined by comparing it with switched capacitor multilevel inverters (MLIs). Finally, a 9‐level prototype is built to verify the theoretical analysis and the practical efficacy of the proposed inverter. [ABSTRACT FROM AUTHOR]

In this work, a quasi-impedance source (QIS) converter is employed as a front-end converter for four-phase switched reluctance (SR) motor drive. The QIS converter is used for dc-link voltage boosting and to enhance the dynamicperformance. The proposed converter can increase the power output in each stage, by increasing the excitation voltage and controlling based on the drive specifications. The demagnetisation terminal is separated from the excitation terminal, and then the voltage is increased further to achieve the quick commutation. Therefore, with the proposed converter, the SR motor can operate with higher voltages at each interval to reach the end goal of faster excitation and commutation. Thus, it eliminates the production of negative torque and reduces the torque ripple. Initially, the steady-state characteristics have been analyzed with the classical asymmetric bridge (CAB) converter and the proposed converter. According to the steady-state characteristics, the proposed converter can provide higher torque and increased power output than the CAB converter. The effectiveness of the proposed converter is validated in a MATLAB/Simulink environment and compared with the CAB converter. Finally, the experimental response is tested using Xilinx SPARTAN 6 FPGA processor and compared with the simulation results. [ABSTRACT FROM AUTHOR]

The first significant contribution made by this article is a novel configuration for MLI that has the potential to enhance voltage. Second, this article's MLI cuts down on the number of components, such as capacitors, switches, diodes, and DC sources. In addition to this, it describes symmetric and asymmetric configurations of DC sources, and the voltage boosting multilevel inverter (VBMLI) will generate 9-level and 17-level output voltages, respectively. The maximum number of levels may be generated by the VBMLI algorithm using either of two extended topologies that each include the necessary mathematical formulas for distinct parameters. To verify the functionality of the proposed 17-level VBMLI, experimental- and simulation-based findings are provided here. [ABSTRACT FROM AUTHOR]

Radio frequency energy harvesting (RFEH) is one form of renewable energy harvesting currently seeing widespread popularity because many wireless electronic devices can coordinate their communications via RFEH, especially in CMOS technology. For RFEH, the sensitivity of detecting low-power ambient RF signals is the utmost priority. The voltage boosting mechanisms at the input of the RFEH are typically applied to enhance its sensitivity. However, the bandwidth in which its sensitivity is maintained is very poor. This work implements a tunable voltage boosting (TVB) mechanism fully on-chip in a 3-stage cross-coupled differential drive rectifier (CCDD). The TVB is designed with an interleaved transformer architecture where the primary winding is implemented to the rectifier, while the secondary winding is connected to a MOSFET switch that tunes the inductance of the network. The TVB enables the sensitivity of the rectifier to be maintained at 1V DC output voltage with a minimum deviation of −2 dBm across a wide bandwidth of 3 to 6 GHz of 5G New Radio frequency (5GNR) bands. A DC output voltage of 1 V and a peak PCE of 83% at 3 GHz for −23 dBm input power are achieved. A PCE of more than 50% can be maintained at the sensitivity point of 1 V with the aid of TVB. The proposed CCDD-TVB mechanism enables the CMOS RFEH to be operated for wideband applications with optimum sensitivity, DC output voltage, and efficiency. [ABSTRACT FROM AUTHOR]

Polyvinylidene fluoride (PVDF) is an emerging method for energy harvesting by fluid motion with superior flexibility. However, the PVDF energy harvester, which has a high internal impedance and generates a low voltage, has a large power transmission loss. To overcome this problem, we propose an impedance-coupled voltage-boosting circuit (IC-VBC) that reduces the impedance of the PVDF energy harvester and boosts the voltage. SPICE simulation results show that IC-VBC reduces the impedance of the PVDF energy harvester from 4.3 MΩ to 320 kΩ and increases the output voltage by 2.52 times. We successfully charged lithium-ion batteries using the PVDF energy harvester and IC-VBC with low-speed wind power generation. [ABSTRACT FROM AUTHOR]

This article proposes a three-phase five-level switched-capacitor active neutral point clamped converter, which can be characterized by voltage boost ability, low-voltage stress across semiconductor devices, and balance of floating capacitor voltage without any auxiliary circuits and/or sensors. Operating principles and modulation scheme of the proposed converter, as well as a comparative analysis with similar topologies are included. Simulation and experimental results for a three-phase prototype are given to demonstrate the feasibility of the proposed five-level converter. [ABSTRACT FROM AUTHOR]

Modular multilevel converter (MMC) and HVdc technology together provide an indispensable solution to integrate offshore wind farms with onshore ac grid. However, the bulky size of MMC and voltage boosting transformers (VBTs) pose a big challenge to keep the footprint and cost of the onshore-platform low. With this background, a full-bridge submodule (SM) modified MMC and a suitably modified switching function are proposed, which utilize the negative SM voltage to achieve ac side voltage boosting. How much negative SM voltages are to be applied across the arms is determined by the group submodule ratio (GSR) parameter, introduced in the switching function. The acquired boosting ability not only shrinks the voltage boosting requirement of VBTs but also reduces the semiconductor switches (upto 10%) and/or the SM count (8%–30%). Analytical solutions derived for the SM capacitor sizing are also presented. The analysis is further utilized to obtain a novel circulating current injection scheme (CCIS), which utilizes phasor analysis to obtain the values of circulating current control parameters. The CCIS suppresses SM capacitor voltage ripple, especially fundamental, and reduces the capacitance requirement by 10%–15% for a wide range of GSR. Representative simulation results are showcased, and the theoretical claims are validated by hardware experiment. [ABSTRACT FROM AUTHOR]

In recent years, focus is given to the increment of the power conversion efficiency of multilevel inverters with integrated voltage boosting characteristics. This can be accomplished by integrating DC/DC converters, featuring partial processing characteristics. In this paper the optimal configuration of the front-end DC/DC converter is proposed considering the lowest power processed by the integrated DC/DC converter for a given asymmetrical five-level topology. It is shown that the Buck-Boost converter is the best candidate solution if the proper configuration is adopted. The operation with asymmetrical output voltage levels offers the ability for variable voltage gain and extension of the input voltage range. However, to avoid low order harmonics due to the asymmetrical levels a modified modulation scheme is proposed. Furthermore, it is proven through rigorous mathematical analysis that efficiency and power density increment can be achieved only if the appropriate mode of operation of the Buck-Boost converter is chosen. The previous statement is supported through an analytical comparison considering the three possible operating modes, proving that DCM operation is the optimal solution. Concluding, a 1.5kVA laboratory prototype is designed with a peak efficiency of 98.7% and experimental results are provided, denoting the converter performance and the accuracy of the preceded analysis.

In this paper, a novel switched capacitors-based seven-level photovoltaic inverter having self-voltage boosting with reduced power switches is analyzed. It has voltage boosting capability with a possibility of 1.5 times of maximum voltage level to input DC voltage. In the proposed topology, higher voltage gain does not impose high voltage stress on any power switches. Therefore, the peak inverse voltage (PIV) of all power switches does not exceed the input source voltage. Furthermore, only a single source is enough, and voltage balancing of capacitors is not required as capacitors are balanced through the charging and discharging phenomenon. A simple modulation technique is used for generating a suitable switching pulses for the inverter. A comparative analysis is presented with other switched capacitors multilevel inverter in terms of the number of power switches, total standing voltage, PIV, and cost function. The closed-loop structure of proposed inverter is investigated with specified controlling and implemented in MATLAB/Simulink and validated through hardware-in-the-loop real-time simulation in OPAL-RT. Additionally, an experimental prototype of the proposed topology in open as well as closed loop is built and tested to validate its efficacy. [ABSTRACT FROM AUTHOR]

Three-phase (3-φ) induction motor drives operated with switched capacitor (SC) inverter circuits offer superior harmonic performance and voltage boosting. The SC network, however, generally requires additional circuitry to precharge the capacitor(s) to prevent inrush current. To obviate the requirement of the extra circuit, an innovative SC precharging scheme is presented, which utilizes the winding inductance of the motor. The inverter circuit is so operated that the motor winding inductance first stores electrical energy from the input dc source and then releases it to the SC. These two actions are continued till the SC is precharged to a voltage equal to the magnitude of the input dc source. The circuit operation during the precharging is similar to the operation of a conventional buck-boost type dc–dc converter. The precharging action is so designed that the voltage of the SC cannot increase further. Therefore, the proposed scheme does not need any voltage sensor. The operation of the circuit during precharging is analyzed extensively to develop a mathematical background for the given method. It is shown that by manipulating the switching frequency during the precharging the precharging time can be controlled as per the user requirements. Various claims are validated using computer simulations and experiments. All the results are presented. [ABSTRACT FROM AUTHOR]

Gate voltage boosting has been routinely used in FPGAs to increase the performance and energy efficiency of pass transistor circuits. The boosting technique is used either alone or in conjunction with level restorers to restore pass transistor outputs to the supply voltage level, which can lead to significant improvement in the power-delay product. Gate voltage boosting is achieved in conventional FPGAs by powering the configuration memory with the boosted voltage and boosted data coming from the configuration memory is directly applied to the gates of the routing multiplexers. In multi-context FPGAs, however, configuration memory data need to pass through the context switches before it can be applied to the routing multiplexers. Passing boosted signals through the context switches can result in significantly higher power consumption, which can be a major concern in multi-context FPGAs. As a result, this work investigates the removal of gate voltage boosting from FPGAs and compares the energy efficiencies of the boosted FPGAs and FPGAs without boosting for multi-context FPGAs. We found that if frequent content switching is required then non-boosted multi-context FPGAs with a larger number of configuration contexts achieve lower power-delay-product compared to boosted multi-context FPGAs. In particular, for single-context FPGAs, boosted FPGAs have 15%–65% lower power-delay product than FPGAs without boosting. Boosted multi-context FPGAs maintain this advantage if the context switching is done infrequently. This advantage, however, reduces if the context switching is done more frequently and, at the same time, boosted FPGAs also become less efficient in terms of power-delay-product as the number of configuration contexts is increased. For ten configuration contexts, FPGAs without boosting can achieve 2%–35% lower power-delay product compared to boosted FPGAs if the context switching is performed every clock cycle and this advantage continues to rise as the number of configuration contexts is increased. Furthermore, FPGAs without boosting also have the advantage of achieving higher logic capacity compared to boosted FPGAs. Under the same power budget, for ten configuration contexts, FPGAs without boosting achieve 1.2–2 times higher logic capacity compared to boosted FPGAs. • Investigated different context switching circuits for MC-FPGAs. • Identified the limitation of the standard context switching design approach. • Non-gate boosted MC-FPGAs achieved lower PDP for frequent context switching tasks. • Proposed non-gate boosted MC-FPGAs for achieving high logic capacity. [ABSTRACT FROM AUTHOR]

A dual‐source switched‐capacitor multilevel inverter (SCMLI) topology utilizing 13 switches, one diode, and two switched capacitors is presented in this paper. The proposed topology is capable of operating in both asymmetrical and symmetrical modes. In asymmetrical mode, it produces 19‐level output voltage, whereas, in symmetrical mode, it produces 13‐level output voltage. The capacitor voltages are self‐balanced in the presented SCMLI topology. A detailed comparative analysis has been carried to show the advantages of the proposed topology in terms of the number of switches, number of capacitors, number of sources, and boosting of the converter with the recently published multilevel inverter topologies. The nearest level control (NLC)‐based algorithm is used for generating switching signals for the IGBTs present in the circuit. The reliability assessment is carried to assess the life span of the proposed SCMLI. Experimental results are obtained for different loading conditions using a laboratory hardware prototype. The fluke‐based power analyzer is used to record the inverter voltage and corresponding THD values at different modulation indexes. The efficiency of the proposed inverter is 97.35% for 200‐W load. [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLIs) have seen significant growth in a variety of medium- to high-power industrial applications and have become a mature and viable solution for renewable energy systems over the past decade. The major concerns of MLIs are the high component count and the buck-type feature of the ac output voltage when used for grid-connected renewable-energy-based sources such as solar photovoltaic (PV) panels. As another option, a switched-capacitor (SC)-based inverter possessing the feature of boost ability is a prime solution to meet the requirements of ac power applications. Integrating an SC network with a neutral-point clamped (NPC) structure makes leakage current alleviation viable for transformerless PV grid-connected systems. In this article, an improved SCMLI based on the NPC structure is proposed to reduce the number of active switches and the number of switches in the charging loop, significantly reducing the power loss. It can generate seven voltage levels with voltage boosting and self-balancing of capacitors within a single-stage power conversion. The working principle of the proposed topology, circuit description, and control technique are presented. Further, the proposed inverter was compared with other recent SC topologies to show its superiority. In the end, a laboratory prototype was developed and tested for the seven-level module under steady-state and dynamic conditions to validate the practical viability of the proposed configuration. The proposed inverter’s maximum efficiency was 97.5% at 1.2 kW rated power.

This paper presents a novel concept of the DC-AC system with the input voltage boost ability, seven-level output voltage modulation, and the input AC current reduction at the double frequency of the output voltage. The system integrates the NPC full-bridge inverter which is composed of four-level legs and an active input voltage balancer (AIVB). The DC-link is composed of three capacitors connected in a series. The source of the energy is connected directly to the middle capacitor while the upper and lower capacitors of the DC-link are charged by the AIVB. The operation of the AIVB leads to balancing of the DC-link voltage and a three-fold boosting of the input voltage. The AIVB utilizes a novel switched-capacitor (SC) topology and can be designed as a low-volume quasi-magneticless converter with a simple open-loop control. One of the proposed methods of the control of the AIVB allows for a double frequency reduction in the input current. The application of the AIVB allows for the use of a seven-level NPC full-bridge (FB) inverter with a simple classic carrier-based PWM which is not applicable in the typical DC-link configurations. This paper presents the converter's concept, its operation, control methods, and the results of simulations and experiments. [ABSTRACT FROM AUTHOR]

Voltage boosting three-level inverters may present a monotonically increasing or decreasing voltage gain when enlarging the pulsewidth modulation (PWM) ratio. To produce a flexible voltage gain, this article proposes a novel three-phase three-level PWM inverter by cascading a traditional two-level three-leg (B6) inverter with half-bridges. The proposed inverter is supplied by an inductive dc-link consisting of a dc source in series with an inductor that is charged by shooting through the half-bridges in the B6 structure. The voltages across the cascaded half-bridges are subsequently boosted, and the output voltage is stepped up due to the cascaded connection. A moderate voltage gain is achieved with proper selections of two modulation variables while maximizing the PWM ratio. In particular, when the two modulation variables are equal, a constant voltage boosting gain of two is maintained irrespective of the PWM ratio. Additionally, low voltages are induced on the components, which facilitates the use of low-voltage devices. The operating principle of the proposed inverter with a modified third-harmonic-injection PWM scheme is presented, followed with theoretical analysis, comparison, and design considerations. Experimental tests on a 1.5-kVA inverter prototype verify its feasibility. [ABSTRACT FROM AUTHOR]

Solar photovoltaic (PV) is the most promising renewable energy source available on Earth. Three topologies based on a switched-inductor capacitor and non-isolated high-step-up Cuk converter have been proposed for solar PV. These topologies of the Cuk converter have higher boosting ability than conventional Cuk and boost converters and can reduce the voltage stress of the main switch. A small voltage rating and on-state resistance can give higher efficiency of the converter. The voltage boosting ability of all three topologies was compared to each other and with a conventional Cuk converter. The boosting capability of the third converter was 11 times at 0.75 duty cycle with a solar PV source. These converters do not use a coupled inductor and transformer, which leads to less volume, reducing coupling/core saturation loss, and thus the cost of the converter. A solar PV system of 12 volts was used for boosting with these converters for analysis of the feasibility of use with renewables. The three topologies of the switched-inductor and switched-capacitor (SLSC) Cuk converter were designed and simulated in MATLAB/Simulink to evaluate their effectiveness. [ABSTRACT FROM AUTHOR]

This research paper proposes a new switched-capacitor topology for the multilevel inverter. The structure has two isolated DC power supplies and a capacitor. Since the topology uses only one capacitor, it eliminates the problem of voltage balancing across the capacitors. This structure produces 13-level output voltage across the load terminals. The structure can be extended using derived generalized equations. A comparative analysis shows the number of components used with respect to other 13-level inverters existing in the literature. The power loss and efficiency of the topology are evaluated and experimentally verified. Moreover, the output voltage and current waveform for the topology is tested for pure resistive, inductive load, the impact of change in modulation index, and impact of the sudden change in load and is simulated and later verified experimentally using a dSPACE-1104 real-time controller. [ABSTRACT FROM AUTHOR]

The conventional neutral point clamped (NPC) multilevel inverter topology needs voltage balancing circuits to balance the dc-link capacitor, the number of component count is high and output voltage is half of the input voltage which increase the size of the source side dc/dc converter in PV applications. In this paper, a new topology of seven level neutral point clamped inverter is developed. The proposed inverter has a self-voltage boosting capability using a floating capacitor to boost the output voltage one and half of the input voltage. In this proposed topology, no additional sensors are required for the floating capacitor voltage stability, which results in minimizing the complexity of designing the inverter. The direct link between the neutral point and the mid-point of the dc-link capacitors significantly reduces the leakage current and common mode voltage in this inverter. A thorough comparison between the developed topology and recent suggested topologies is carried out which set the benchmark for the proposed one due to its lower switch count and higher voltage gain. The proposed topology is verified in simulation and prototype hardware model and results are discussed with dynamic load variations. The efficiency of the inverter is 97.1% @200W and low as 88.1 % @ inductive load. The voltage THD is 17.01% for simulation and 19.3% I for experimental is results.

Cascaded multilevel inverter (CMI) produces a step-up output voltage by series-connection of several submodules (SMs) supplied by isolated dc sources, which can be implemented by photovoltaic (PV) sources. The unbalanced power provided by different PV sources may however distort the output voltage. To use a single dc source while retaining the voltage boosting, this article proposes a novel CMI based on a four-switch SM. It is conditioned by an input inductor, which discharges with boosted voltages across the SMs. Furthermore, a continuous input current is achieved by the inductor. The proposed inverter can be extended to higher voltage-level operations using capacitors to supply its extended SMs. To avoid switched-capacitive charging, a two-phase configuration where capacitors are directly charged by the inductive input current is presented. The voltages of capacitors are well balanced at the same average value and feature a similar ripple. The operating principles and pulsewidth modulation scheme of the two-phase inverter are described. Theoretical analysis, calculations, and comparisons with the prior-art CMIs illustrate the superiorities of the proposed inverter. Simulation and experimental results agree well with each other and verify the feasibility of the proposed inverter for PV power applications. [ABSTRACT FROM AUTHOR]

This paper presents a new single-source three-phase seven-level inverter with an inherent three-time voltage boosting capability for medium-voltage applications. The proposed topology is comprised of series connection of two switched-capacitor (SC) networks with an added half-bridge module per phase. Each of such integrated SC networks requires a single capacitor associated with three active power switches. The three-time voltage boosting feature of the proposed topology can reduce the dc-link voltage requirements by 50% in comparison to the traditional neutral point clamped (NPC), flying capacitors, active NPC (ANPC), hybrid clamped ANPC, and cascaded H-bridge topologies, and 75% to advanced ANPC topologies. It can also reduce the number of required switches and capacitors as well as their voltage stresses compared to those state-of-the-art topologies reported in the literature. By integrating “n” number of added SC networks in the proposed seven-level basic topology, the number of output voltage levels can be extended to 2n+3 per phase. A finite control set model predictive control algorithm is also derived to control the converter in both the active and reactive power exchanges modes without distorting the generated grid current quality. The capacitor voltage balancing is inherent in the proposed topology, and thus, there is no need for any additional voltage balancing circuit, which further reduces the control complexity. The performance of the proposed topology and its control algorithm are validated by several measurement results. [ABSTRACT FROM AUTHOR]

Radio frequency energy harvesting (RFEH) is one form of renewable energy harvesting currently seeing widespread popularity because many wireless electronic devices can coordinate their communications via RFEH, especially in CMOS technology. For RFEH, the sensitivity of detecting low-power ambient RF signals is the utmost priority. The voltage boosting mechanisms at the input of the RFEH are typically applied to enhance its sensitivity. However, the bandwidth in which its sensitivity is maintained is very poor. This work implements a tunable voltage boosting (TVB) mechanism fully on-chip in a 3-stage cross-coupled differential drive rectifier (CCDD). The TVB is designed with an interleaved transformer architecture where the primary winding is implemented to the rectifier, while the secondary winding is connected to a MOSFET switch that tunes the inductance of the network. The TVB enables the sensitivity of the rectifier to be maintained at 1V DC output voltage with a minimum deviation of −2 dBm across a wide bandwidth of 3 to 6 GHz of 5G New Radio frequency (5GNR) bands. A DC output voltage of 1 V and a peak PCE of 83% at 3 GHz for −23 dBm input power are achieved. A PCE of more than 50% can be maintained at the sensitivity point of 1 V with the aid of TVB. The proposed CCDD-TVB mechanism enables the CMOS RFEH to be operated for wideband applications with optimum sensitivity, DC output voltage, and efficiency.

Polyvinylidene fluoride (PVDF) is an emerging method for energy harvesting by fluid motion with superior flexibility. However, the PVDF energy harvester, which has a high internal impedance and generates a low voltage, has a large power transmission loss. To overcome this problem, we propose an impedance-coupled voltage-boosting circuit (IC-VBC) that reduces the impedance of the PVDF energy harvester and boosts the voltage. SPICE simulation results show that IC-VBC reduces the impedance of the PVDF energy harvester from 4.3 MΩ to 320 kΩ and increases the output voltage by 2.52 times. We successfully charged lithium-ion batteries using the PVDF energy harvester and IC-VBC with low-speed wind power generation.

This article presents a novel cascaded multilevel inverter as an alternative to the cascaded H-bridge (CHB). By adopting two H-bridges integrated with two inductors and two power switches, the proposed topology is able to generate a five-level voltage with merely a single dc source. Voltage-boosting capability is guaranteed despite its single-stage operation. A corresponding modulation technique is also established to charge the boost inductors with a constant duty-cycle while simultaneously generating a five-level ac voltage. Therefore, the proposed topology outperforms the CHB in reducing the isolated dc source count, enhancing the voltage gain, and lowering the dc source voltage magnitude. In addition, the modularity is preserved, where the proposed topology can be extended by cascading multiple modules. The operation and feasibility of the proposed cascaded multilevel inverter is analyzed and validated through simulation and experimental results. [ABSTRACT FROM AUTHOR]

Switched-capacitor-based multilevel inverters have been gaining increasing attention in recent years in view of their voltage-boosting capability and capacitor self-balancing properties. However, the existing topologies, which comprise frontend switched-capacitor cells and a backend H-bridge, result in longer discharging duration in some of their switched-capacitors. In addition, the adoption of backend H-bridge introduces common-mode voltage and necessitates multiple dc sources for voltage level extension. To resolve these problems, this article proposes a novel topology comprises a T-type inverter and n cascaded switched-capacitor cells. It requires only a single dc source and it manages to mitigate the common-mode voltage by connecting the neutral of ac output to the mid-point of dc link. All switched-capacitors in the proposed topology are ensured to be charged for at least half of the fundamental period to alleviate the capacitor voltage ripples and current spikes. The operation of the proposed topology is analyzed and experimental results are presented for validation. [ABSTRACT FROM AUTHOR]

This paper proposes a series of new control methods for single-phase Z-source inverters. A detailed description of the concept and principle of each method is first presented, then a comparison among them is conducted comprehensively. Afterwards, an optimized closed-loop control scheme with better harmonic elimination performance is derived. Experimental results obtained from a 1kW un-isolated Z-source inverter prototype have demonstrated the effectiveness of the proposed control method. Compared to the conventional boost control, the proposed scheme has better performance with reduced harmonics, more flexible voltage gain, and simple algorithm.

Multilevel inverters (MLIs) with self-balanced switched-capacitors (SC) have received wide recognition for increasing the reliability and efficiency of renewable energy and high-frequency power distribution systems. This article presents a new SC MLI structure using a reduced number of components. The proposed dual-source SC MLI can be extended in various ways to increase the voltage levels at the output. The SCs are self-balanced by using a suitable charging–discharging pattern, and thereby, voltage boosting is achieved. The operational analysis and features of the proposed 25-level MLI are delineated in detail. Comparative analysis with state-of-the-art MLIs in terms of the number of components, voltage stress, and cost factor demonstrate the merit of the proposed extendable SC MLIs. Extensive simulation of the proposed MLI structure is performed on the MATLAB/Simulink environment using both the low and high switching frequency control schemes. Furthermore, simulation results are validated experimentally by developing a prototype of the proposed MLI under load variations, frequency change condition, and variation in the modulation index. [ABSTRACT FROM AUTHOR]

Boost type switched-capacitor inverter topologies are highly suitable for photovoltaic based distributed power generation and electric vehicle applications. This brief proposes a new single-stage boost type inverter topology with features of self-voltage balancing capability of floating capacitors (FCs), seven-level (7L) stepped output voltage generation with peak output voltage three times higher than the input voltage. The modes of operation are discussed in detail emphasizing the self-voltage balancing. Further, the proposed topology uses less number of semiconductor devices. A detailed comparison with other recent 7L inverter topologies is presented to attest to the merits of the proposed topology concerning a reduced number of components. Finally, a laboratory prototype is employed to validate the proposed topology’s operability, and the obtained experimental results are presented. [ABSTRACT FROM AUTHOR]

Summary: Multilevel inverters are very popular in renewable energy applications. These inverters produce output voltages close to sinusoidal and have lower harmonics as compared to the conventional two‐level inverters as it also helps in reducing the size of the filter, thus makes the circuitry less complicated. In conventional multilevel inverter topologies, the number of devices increases with the increase of the number of output voltage levels, which in turn makes circuitry bulky and costly. Further, the boosting feature of the input voltage is also necessary for the application of multilevel inverters with renewable energy. Therefore, to reduce the count of devices, losses, and rating of devices, various switched‐capacitor multilevel inverter topologies are proposed. Switched‐capacitor multilevel inverter topologies (SCMLIs) can generate multiple voltage levels along with high voltage gain with a minimum number of devices. This paper gives a detailed overview of the recently introduced SCMLIs. The different SCMLIs have been categorized based on the number of levels and voltage gains. A detailed comparison has been introduced in this paper. Finally, few SCMLI topologies have been experimentally validated using the experimental results. [ABSTRACT FROM AUTHOR]

A new boosting multilevel inverter with switched-capacitors is presented in this brief. By employing 13 switches, two diodes, and three capacitors, a 13-level voltage waveform is synthesized. The capacitor voltages are self-balanced as they are connected in parallel with the input voltage source for several instances in every fundamental cycle. A simple logic gate based pulse-width modulation scheme ensuring power balance among the capacitors is presented. Experimental results obtained from a laboratory prototype are presented for validating the operation and ability of the proposed inverter to boost the input by a factor of six. Finally, a detailed comparison with existing topologies proves the cost-effectiveness, a simpler structure requiring lesser space and footprint area of the proposed topology. [ABSTRACT FROM AUTHOR]

In this brief, a new cross-connected compact switched capacitor (C3SC) cell is introduced for multilevel inverter applications. The proposed CCS cell uses four switches and two diodes for interconnecting the input dc source and floating capacitors (FCs). A nine-level inverter is derived with the proposed C2SC cell requiring only ten switches and two FCs. The proposed C3SC cell-based MLI is self-balancing and has a voltage gain of two. All the switches of the proposed topology have a maximum blocking voltage within the input dc voltage (v $_{in}$) value. The operating principle is detailed, and a simple logic gate based gate pulse generation scheme is presented. Detailed simulations and experimental results obtained from an 850 W prototype with several test cases are presented to validate the operation of the proposed topology. Finally, a detailed comparative assessment is performed with other recent SCMLIs to demonstrate the merits and superiority of the proposed topology. [ABSTRACT FROM AUTHOR]

This paper presents a new topology of switched reluctance motor (SRM) drives for plug-in hybrid electric vehicles. Six operating modes can be achieved as a result. Three of those modes are applied for driving and the others for charging. During the driving mode, the topology can be converted to a fourlevel one. During the charging mode, two battery packs are charged in parallel with the boost circuit by the external ac source or generators. The main contributions of the proposed topology are as follows. First, a four-level converter is formed by adopting different ways of connection (series or parallel) of the two battery packs (or the two capacitors), which can accelerate the excitation and demagnetization procedures of SRMs. Moreover, the topology contributes to decreasing the switching losses and extending the constant torque region to improve the drive performance as well. Second, the state of charge of the two battery packs (or the voltages of two capacitors) can keep balance on their own by parallel operation of the two battery packs. Furthermore, a detailed comparison between two drive modes of the proposed topology and asymmetric half bridge inverters is undertaken with simulation and experimental studies, the results of which demonstrate the validity of the proposed topology.

The cascaded H-bridge multilevel inverter (MLI) requires separate isolated dc sources to generate more than three voltage levels and to generate higher output voltage. This paper proposes a new MLI topology that requires only one dc source and is capable of generating seven voltage levels with triple voltage boosting gain. Three H-bridges are interconnected through two bidirectional voltage blocking switches to enable the integration of two switched-capacitors. Unlike the existing two-stage structure switched-capacitor-based MLI, the proposed MLI is a single-stage topology. It alleviates the voltage stress across switches such that low voltage stress of not more than the dc source voltage is ensured on all switches. In addition, capacitors voltage balancing is achieved automatically during operation. The operation of the proposed MLI is analyzed followed by verification through simulation and experimental test of a low power/voltage prototype.

This brief presents a novel seven-level (7L) inverter topology for grid-connected renewable applications. It consists of ten active switches and one inner flying-capacitor unit forming a structure similar to conventional active neutral point clamped inverter. The proposed unique arrangement reduces the number of active, passive components and it does not require any sensor to balance the floating capacitor voltage, thereby reduces cost and complexity in the control system design. In addition, compared to major conventional 7L inverter topologies, the proposed topology is capable of boosting the input voltage by a factor of 1.5, thereby, eliminating the need for an intermediate boosting stage. In other words, it reduces the dc-link voltage requirement by 50%. To prove the advantage of the proposed topology over other recent topologies, a comparative study in terms of power components and cost is presented. The operation and performance of the proposed topology for various loading conditions are validated through experimental tests and measurements. [ABSTRACT FROM AUTHOR]

Summary: This paper proposes an improved "K" type seven‐level switched capacitor inverter topology. The proposed topology consists of eight active switches, one floating capacitor, and two dc‐link capacitors. The floating capacitors are charged and discharged in each half‐cycle to maintain the capacitor voltage with the same value of the input voltage. The floating capacitor voltage is self‐balanced, and the output voltage is 1.5 times higher than the input voltage. To prove the superiority of the proposed topology, it is compared with the existing seven‐level inverters in terms of maximum voltage stress on the switch and required the number of power components. The simulation and experimental validation are carried out for 1.6 kW, 50 Hz using a laboratory‐based setup with a switching frequency of 5 kHz. The results are discussed highlighting the performance of the proposed topology for the dynamic load variations at different modulation indices. Both simulation results and experimental results have good agreement in terms of voltage balancing of flying capacitor. [ABSTRACT FROM AUTHOR]

The switched-capacitor-based cascaded multilevel inverters (CMI) have been emerging due to their voltage boosting capability. Unfortunately, they suffer from impulse charging current and nonuniform operation. This article presents a topology termed as dual-T-type five-level CMI to resolve these problems without compromising the desirable voltage boosting characteristic. The main idea is to integrate a half bridge and an inductor to soft charge a capacitor that is connected in series with the dc source. The capacitor enables the voltage gain boosted to two, while the control of eight power switches that constitutes a dual-T structure enables five voltage levels generation. In addition, uniform operation is achieved for cascaded extensions. The operating principle of the proposed topology is analyzed and elaborated. For validation, simulation, and experimental results of a prototype are presented. [ABSTRACT FROM AUTHOR]

Various self-powered devices employ energy-harvesting technology to capture and store an ambient energy. The photovoltaic (PV) cell is one of the most preferred approaches due to its potential for on-chip integration. Although serial connection of multiple PV cells is commonly required to obtain a sufficiently high voltage for circuit operation, a voltage boosting with serially stacked PV cells is limited in a standard bulk CMOS process because all the PV cells are intrinsically connected to the common substrate. It is possible to increase the output voltage by stacking multiple PV cells with a large area ratio between stages. However, nonoptimal design results in a poor conversion efficiency or a limited open-circuit voltage, making it unsuitable for practical applications. This article proposes a stacking structure and its optimal design method for PV cell stacking in a triple-well CMOS process. The proposed approach utilizes an additional current-sourcing photodiode and an optical filter, which allow high voltage generation without a significant efficiency degradation. The test chip with four-stage stacked PV cells was fabricated using a 0.25-μm standard triple-well CMOS process. The experimental results demonstrate an output voltage of 1.6 V and an electrical power of 263 nW/mm2 under an incident illumination with an intensity of 96~μW/mm2, achieving a responsivity of 1.91 mA/W and a conversion efficiency of 0.27%. [ABSTRACT FROM AUTHOR]

Conventional active-neutral-point-clamped (ANPC) inverters exhibit low voltage gain that inherently leads to a high dc-link voltage requirement. An improved ANPC inverter that is capable of generating five voltage levels has recently reduced the dc-link voltage twofold to achieve unity gain. This led to the development of a single-stage dc–ac power converter with no frontend boost dc–dc converter. This article proposes novel ANPC inverters capable of unity or boosted voltage gain while generating higher voltage levels. The first topology can provide a voltage gain of 1.5 and extends the number of levels to seven by incorporating only one additional switch. The topology can also be extended by adding three switches and one floating capacitor to generate nine levels with unity voltage gain, or 11 levels with a voltage gain of 2.5. The proposed ANPC inverters and their operations are comprehensively discussed. Experimental results are provided to validate the feasibility of the proposed ANPC inverters. [ABSTRACT FROM AUTHOR]

The conventional three-level inverter only has voltage buck capability. The quasi-Z-source three-level T-type inverter (QZS 3LT $^2$ I) has been proposed to realize voltage buck–boost operation. In this paper, we further propose a novel modulation scheme for the QZS 3LT $^2$ I to realize voltage boosting, reduce the common-mode voltage (CMV), and control the neutral-point voltage balance simultaneously. The proposed scheme adopts a large vector, a medium vector, a small vector with low CMV magnitude, a zero vector, and a shoot-through vector to generate the output voltage. According to sector number and neutral-point voltage difference, a p-type or n-type small vector with low CMV magnitude is properly selected to balance the neutral-point voltage. Shoot-through states are inserted within zero vector to boost the dc input voltage without affecting the ac output voltage. Dwell times of basic vectors are calculated through the revised volt–second balance equation. Furthermore, a coordinate control strategy between neutral-point voltage balance and voltage boosting is proposed. Doing so, the CMV magnitude can be restricted within one-sixth of dc-link voltage and neutral-point voltage imbalance can be effectively mitigated. The effectiveness of the proposed scheme is verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

In this brief, a seven-level (7L) improved packed U-cell (IPUC) inverter with reduced power electronic components is proposed. The presented IPUC inverter has low voltage stress on switches and is capable of voltage boosting. A new voltage balancing method based on logic form equations is developed for regulating the inherent floating capacitor voltage to half the input dc voltage. The proposed 7L IPUC is compared with other state-of-the-art 7L inverters in terms of number of IGBTs, blocking voltage, and driver circuits for attesting its superior merits. The performance of the proposed voltage balancing is verified through a laboratory prototyped 7L IPUC inverter considering varying load conditions and the corresponding results are elucidated. [ABSTRACT FROM AUTHOR]