Full-Chip Power Supply Noise Time-Domain Numerical Modeling and Analysis for Single and Stacked ICs.

In this paper, a distributed circuit model for on-die power distribution network in single and 3-D ICs is developed, and a set of difference equations are derived based on the circuit model and numerically solved using the finite-difference method. Both IR-drop and simultaneous switching noise, two components of power supply noise (PSN), are iteratively solved in time domain, thereby enabling a transient analysis of PSN. Under the assumptions that on-die power/ground pads, power density, and decoupling capacitors are uniformly distributed, PSN within a unit cell is accurately simulated with <1% error compared with HSPICE simulation. By reducing modeling grid fineness, the numerical modeling approach is applied to a full chip that has multiple blocks with nonuniform power/ground pads, power density, and decoupling capacitance density. Based on full-chip modeling, the PSN distribution of a two-die stack is simulated, and the impact of increasing decoupling capacitance and power/ground pads is investigated. [ABSTRACT FROM PUBLISHER]