A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS.

This paper presents a 44.2-mW 3.2-GHz 3-port register file (RF) that demonstrates measured operation from 1.2 V down to 0.4 V. The 32-entry \times \,32 -bit/word 2-read/1-write RF is fabricated in TSMC 65-nm low-power low threshold voltage (low- \text {V}_{\mathrm {t}} ) CMOS process. A four-transistor read port is presented that permits the design of low-capacitance dynamic local bitlines (LBLs). Switching power in the LBLs and the LBL precharge buffer is thereby reduced. Based on extensive simulation results, the proposed read port is recommended for use in wide-worded RFs, which employ a wide dynamic-OR structure at the LBL stage. The proposed RF outperforms the conventional design in terms of power consumption for frequencies exceeding 3-GHz. The read port exploits intrinsic capacitive coupling to achieve robust operation over a wide voltage range. The architecture of the read port simultaneously enhances robustness of the dynamic bitline by 58.8% as compared to the conventional low- \text {V}_{\mathrm {t}}$ bitline. [ABSTRACT FROM PUBLISHER]