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Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node.

Authors :
Jang, Doyoung
Yakimets, Dmitry
Eneman, Geert
Schuddinck, Pieter
Bardon, Marie Garcia
Raghavan, Praveen
Spessot, Alessio
Verkest, Diederik
Mocuta, Anda
Source :
IEEE Transactions on Electron Devices. Jun2017, Vol. 64 Issue 6, p2707-2713. 7p.
Publication Year :
2017

Abstract

In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and nanowire transistors (NW-FETs) for sub-7-nm node. The band structure calculated technology computer aided design results show comparable intrinsic performance to FinFETs at same channel cross section. On top of that, dc and RO are evaluated by taking into account electrostatics, parasitic components, and layout configurations. The NSH-FETs show an advantage in drive current with the NSH width but their RO performance is limited by the device capacitance. The multiple narrow NSH-FET shows ~5% higher drive current compared to the NW-FET at similar subthreshold swing, allowing heavier capacitive loaded circuit. In addition, NSH-FETs can provide the device design freedom from aggressive fin pitch scaling. [ABSTRACT FROM PUBLISHER]

Details

Language :
English
ISSN :
00189383
Volume :
64
Issue :
6
Database :
Academic Search Index
Journal :
IEEE Transactions on Electron Devices
Publication Type :
Academic Journal
Accession number :
124146834
Full Text :
https://doi.org/10.1109/TED.2017.2695455