A Comprehensive Study of a Single-Transistor Latch in Vertical Pillar-Type FETs With Asymmetric Source and Drain.

The single-transistor latch in vertical pillar-type FETs with asymmetric source and drain (S/D) was investigated for capacitorless one transistor dynamic random access memory (1T-DRAM). The asymmetric S/D is produced by the different energies of ion implantation at different depths of the pillar. The window of latch voltage ($\Delta {V}_{L}$), which is the difference between the latch-up voltage (${V}_{\textit {LU}}$) and latch-down voltage (${V}_{\textit {LD}}$), was dominantly governed by ${V}_{\textit {LD}}$. Fluctuation in the $\Delta {V}_{L}{(}{=}{V}_{\textit {LU}} - {V}_{\textit {LD}}$) is mainly induced by different series resistances (${R}_{\textit {SD}}$). The variation in ${R}_{\textit {SD}}$ becomes increasingly fatal to the stable operation of a 1T-DRAM with a smaller diameter; therefore, uniform control of ${R}_{\textit {SD}}$ is very important for the read operation in 1T-DRAM. In addition, the doping concentration of the source should be high for wide $\Delta {V}_{L}$. [ABSTRACT FROM AUTHOR]