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Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications.
- Source :
-
AEU: International Journal of Electronics & Communications . May2019, Vol. 104, p10-22. 13p. - Publication Year :
- 2019
-
Abstract
- This work presents a half-select free 12T SRAM cell with Data-Dependent Feedback Cutting approach to improve the write ability and isolated read path to enhance the read stability. The enhanced read and write ability is 1.95 × and 2.84 × larger respectively than that of the conventional 6T cell at 0.4 V. The half-select free behavior of proposed cell using the cross-point read/write structure facilitates the bit-interleaving memory architecture to effectively reduce the multi-bits soft error occurrence. The incorporated PMOS stacking effect in inverter pairs of the proposed cell offers the reduced leakage power which is 0.59 × to that of 6T, at 0.4 V supply. To further minimize the leakage power at array level, the bit lines between two adjacent cells have been shared that consumes only 0.38 × leakage power than that of the conventional 6T array for a 1 KB macro. Moreover, a Reconfigurable FPGA architecture is proposed for low power applications. The simulated static and active power consumption of 12T SRAM based reconfigurable FPGA is 0.22 × and 0.45 × when compared with the regular 12T FPGA. Finally, a Double Adjacent-bits Error Detection and Correction (DAEDC) scheme is suggested for the proposed bit-interleaved 12T SRAM array, to reduce the soft error effects. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 14348411
- Volume :
- 104
- Database :
- Academic Search Index
- Journal :
- AEU: International Journal of Electronics & Communications
- Publication Type :
- Academic Journal
- Accession number :
- 136348163
- Full Text :
- https://doi.org/10.1016/j.aeue.2019.02.018