Power-Speed Trade-Offs in Design of Scaled FET Circuits Using C/IDS Methodology.

An analytical approach to evaluate performance of analog integrated circuits and make a comparative study in different technology nodes is presented. To provide closed-form solutions, this article proposes using $\mathscr {C} = \text {C}/\text {I}_{\text {DS}}$ as an independent design variable, where C refers to any physical or parasitic capacitance associated with a Field-Effect Transistor (FET) biased at IDS. The proposed $\mathscr {C}$ -based methodology is used to study speed versus power trade-offs in both continuous-time (CT) and discrete-time (DT) circuits. Predictive Technology Models (PTMs) have been used to study performance of both MOSFET and FinFET (i.e. FET) devices in different technology nodes. This analysis shows that FinFET transistors exhibit a wider medium-inversion region compared to MOSFET devices, making them more convenient for high-speed and low-power designs. Additionally, this study proves that a lower sub-threshold slope factor results in an improved energy-efficiency of analog circuits. [ABSTRACT FROM AUTHOR]