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High-performance hardware architecture of a robust block-cipher algorithm based on different chaotic maps and DNA sequence encoding.

Authors :
Amdouni, Rim
Gafsi, Mohamed
Guesmi, Ramzi
Hajjaji, Mohamed Ali
Mtibaa, Abdellatif
Bourennane, El-Bay
Source :
Integration: The VLSI Journal. Nov2022, Vol. 87, p346-363. 18p.
Publication Year :
2022

Abstract

Nowadays, secure digital data in store and transmission is an important issue. Cryptographic methods are widely used to provide optimal security for multimedia data. In this paper, a good performance implementation of a strong block-cipher system is proposed. This article's contribution is to develop a new method to block-cipher hardware system based on DNA biological properties and various 3D chaotic maps. In this scheme, the high-level security is achieved by chaotic sequences generated by a robust chaos-based PRNG based on the Lorenz, Chua, Rossler, and Chen chaotic maps. The latter is used to generates high-quality keys that are applied for encryption. Thus, a high-security block cipher approach for encrypting and decrypting images has been developed. To increase the confusion process complexity, several biological operations, such as DNA-XOR, are added to the encryption process. Furthermore, a novel hardware architecture of the proposed block-cipher system is put forward. The latter achieves a low power consumption, good frequency of 192.813 MHz and high throughput of 24,576,153 Mbps built. The security analysis demonstrates that the cryptosystem provides effective security. The proposed PRNG validated successfully both the NIST SP 800–22 test suite and the U01-Test. Various tests are performed, such as statical tests, phase analysis and differential attacks applied to different images. A comparison of the proposed algorithm with several newly developed encryption algorithms demonstrates that our system generates good results. • Creating a robust PRNG based on multiple chaotic systems. • Using confusion and diffusion features to design a fast and safe block-cipher algorithm. • Proposing and FPGA-zynq implementation of the block-cipher hardware architecture. • Experimenting with ordinary images with the aim to assess the effectiveness of the suggested block-cipher system against the most known attacks. • Evaluating the performances of the hardware cryptosystem and comparing the obtained results to comparable related works. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
01679260
Volume :
87
Database :
Academic Search Index
Journal :
Integration: The VLSI Journal
Publication Type :
Academic Journal
Accession number :
158930874
Full Text :
https://doi.org/10.1016/j.vlsi.2022.08.002