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A 10-Gbps CTLE design using split-length input pair MOS Transistors.
- Source :
-
International Journal of Electronics Letters . Dec2023, Vol. 11 Issue 4, p449-458. 10p. - Publication Year :
- 2023
-
Abstract
- The equaliser is an indispensable block inside the receiver in Serial Link systems. It is used to moderate the high-frequency loss of the signal in the channel. A new technique is described to improve the performance of the Continuous-Time Linear Equaliser (CTLE). This technique utilises split-length device (SLD) in order to boost the output impedance of the SLD. The proposed CTLE is designed and simulated in 65 nm CMOS technology. Post-layout simulation results demonstrate that the proposed technique has more peaking than conventional CTLE by an order of 1.5 dB at Nyquist frequency. The Proposed design has a vertical eye-opening of 220 mV and a horizontal eye-opening of 0.35 UI. It consumes 1.56 mW from a 1.2 V supply. A FoM of 13.1 fJ/bit/dB is achieved. [ABSTRACT FROM AUTHOR]
- Subjects :
- *NYQUIST frequency
*TRANSISTORS
Subjects
Details
- Language :
- English
- ISSN :
- 21681724
- Volume :
- 11
- Issue :
- 4
- Database :
- Academic Search Index
- Journal :
- International Journal of Electronics Letters
- Publication Type :
- Academic Journal
- Accession number :
- 174540096
- Full Text :
- https://doi.org/10.1080/21681724.2022.2117850