基于优化 BPNN 的 FPGA 内嵌高速接口总抖动预测方法.

In view of the problem that ATE(Automated Test Equipment) can not measure the total jitter of FPGA (Field-Programmable Gate Array) embedded high-speed interface directly, this study presents a method to predict the total jitter of high-speed interface based on optimized BPNN(Back Propagation Neural Network). The GA-BP neural network is formed to optimize the initial weight and parameter seeking process of BPNN using the strong global search ability of GA(Genetic Algorithm), and improve the accuracy of predicting the total jitter. The GA_BP total jitter prediction model was constructed using MATLAB software to predict and optimize the screened jitter data. The experimental results show that compared with the non-optimized BP neural network and the traditional Elman neural network prediction model, the mean square error of the GA_BP prediction model is declined by 75.5% and 88.0%, and the number of iterations is reduced by 68.0% and 59.8%, respectively. It indicates that the proposed GA_BP model has higher prediction accuracy and iteration efficiency, and can be applied to total jitter production test in ATE. [ABSTRACT FROM AUTHOR]