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Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation.
- Source :
-
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems . Nov2006, Vol. 25 Issue 11, p2427-2436. 10p. 4 Black and White Photographs, 2 Charts, 3 Graphs. - Publication Year :
- 2006
-
Abstract
- Under inter-die and intra-die parameter variations, the delay of a pipelined circuit follows a statistical distribution. This paper presents analytical models to estimate yield for a pipelined design based on delay distributions of individual pipe stages. Using the proposed models, it is shown that a change in logic depth and an imbalance between stage yields can improve the design yield and the area of a pipeline a circuit. A novel statistical methodology is developed to enhance yield of a pipelined circuit under an area constraint. Based on the concept of area borrowing, the results show that incorporating a proper imbalance among stage areas in a four-stage pipeline improves design yield up to 15.4% for the same area (and reduces area up to 8.4% under a yield constraint) compared with a balanced design. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 02780070
- Volume :
- 25
- Issue :
- 11
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
- Publication Type :
- Academic Journal
- Accession number :
- 22934197
- Full Text :
- https://doi.org/10.1109/TCAD.2006.873886