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An FPGA-Based Linear All-Digital Phase-Locked Loop.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Sep2010, Vol. 57 Issue 9, p2487-2497. 11p. - Publication Year :
- 2010
-
Abstract
- In this paper, an all-digital phase-locked loop (ADPLL) is presented, and it is implemented on a field-programmable gate array. All components like the phase detector (PD), oscillator, and loop filter are realized as digital discrete-time components fed from analog-to-digital converters. The phase detection is realized by generating first an analytic signal using a compact implementation of the Hilbert transform and then computing the instantaneous phase with the CORDIC algorithm. A phase-unwrap component was realized, which extends the linear range of the PD, so that the linear model is valid in the full frequency range. This property leads to a constant lock-in time for arbitrary frequency changes. An analytic solution for the lock-in frequency range and the stability range including processing delays is given. All relations to design an ADPLL of the presented structure are derived. A detailed example application of an ADPLL designed as an offset local oscillator is given. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 57
- Issue :
- 9
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 62330776
- Full Text :
- https://doi.org/10.1109/TCSI.2010.2046237