Memory and computation efficient hardware design for a 3 spatial and temporal layers SVC encoder.

Spatial and temporal scalability in Scalable Video Coding (SVC) compression enables a video encoder to generate bit streams efficiently for various resolutions and frame rates. However, doing this requires more complex computations and greater memory bandwidth than H.264/AVC compression. In this paper, the performance and memory bandwidth for a SVC hardware encoder with three spatial and temporal layers are analyzed. Based on the analysis, a novel method is proposed for the source and interlayer data load. Experimental results show that the memory bandwidth is reduced by 77%. Furthermore, the memory access latency of the source data for the base layer is reduced by creating a data load for the base layer overlap with the execution of the enhancement layer. To satisfy the latency requirement, a mode pre-decision algorithm for a hardware SVC encoder is proposed. It reduces the computation of the fractional motion estimation (FME) and the inter-layer residual prediction by 80%. Simulation results show that the proposed methods decrease the BD-PSNR by 0.05 dB and increase the BD-BR by 1.64%, an amount that can be considered negligible in terms of degradation, while an encoding speed of 30 fps for Full HD (1920?1080) videos is achieved at an operating clock frequency of less than 200 MHz.1 [ABSTRACT FROM AUTHOR]