Back to Search
Start Over
Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology.
- Source :
-
IEEE Transactions on Electron Devices . Oct2012, Vol. 59 Issue 10, p2626-2634. 9p. - Publication Year :
- 2012
-
Abstract
- An ultralow-leakage power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide devices and with silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. By reducing the voltage difference across the gate oxide of the devices in the ESD detection circuit, the proposed power-rail ESD clamp circuit can achieve an ultralow standby leakage current. In addition, the ESD-transient detection circuit can be totally embedded in the SCR device by modifying the layout structure. From the measured results, the proposed power-rail ESD clamp circuit with an SCR width of 45 \mu\m can achieve 7-kV human-body-model and 350-V machine-model ESD levels under the ESD stress event while consuming only a standby leakage current in the order of nanoamperes at room temperature under the normal circuit operating condition with 1-V bias. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 59
- Issue :
- 10
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 82709798
- Full Text :
- https://doi.org/10.1109/TED.2012.2209120