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Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology.
- Source :
-
Sensors (Basel, Switzerland) [Sensors (Basel)] 2021 Dec 24; Vol. 22 (1). Date of Electronic Publication: 2021 Dec 24. - Publication Year :
- 2021
-
Abstract
- The design of advanced miniaturized ultra-low power interfaces for sensors is extremely important for energy-constrained monitoring applications, such as wearable, ingestible and implantable devices used in the health and medical field. Capacitive sensors, together with their correspondent digital-output readout interfaces, make no exception. Here, we analyse and design a capacitance-to-digital converter, based on the recently introduced iterative delay-chain discharge architecture, showing the circuit inner operating principles and the correspondent design trade-offs. A complete design case, implemented in a commercial 180 nm CMOS process, operating at 0.9 V supply for a 0-250 pF input capacitance range, is presented. The circuit, tested by means of detailed electrical simulations, shows ultra-low energy consumption (≤1.884 nJ/conversion), excellent linearity (linearity error 15.26 ppm), good robustness against process and temperature corners (conversion gain sensitivity to process corners variation of 114.0 ppm and maximum temperature sensitivity of 81.9 ppm/°C in the -40 °C, +125 °C interval) and medium-low resolution of 10.3 effective number of bits, while using only 0.0192 mm2 of silicon area and employing 2.93 ms for a single conversion.
- Subjects :
- Electric Capacitance
Silicon
Technology
Equipment Design
Subjects
Details
- Language :
- English
- ISSN :
- 1424-8220
- Volume :
- 22
- Issue :
- 1
- Database :
- MEDLINE
- Journal :
- Sensors (Basel, Switzerland)
- Publication Type :
- Academic Journal
- Accession number :
- 35009664
- Full Text :
- https://doi.org/10.3390/s22010121