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3.21 ps ECL gate using InP/InGaAs DHBT technology.

Authors :
Ishii, K.
Nosaka, H.
Ida, M.
Kurishima, K.
Shibata, T.
Source :
Electronics Letters (Institution of Engineering & Technology); 10/2/2003, Vol. 39 Issue 20, p1434-1436, 3p
Publication Year :
2003

Abstract

A new circuit configuration for an emitter-coupled logic (ECL) gate that can reduce propagation delay time has been demonstrated. Nineteen- stage ring oscillators were fabricated using InP/InGaAs double-hetero- junction bipolar transistors (DHBTs) with cutoff frequency fr and maximum oscillation frequency f[SUBmax] of about 232 and 360 GHz, respectively, to evaluate the speed performance of the proposed ECL gate. The minimum propagation delay is 3.21 ps/gate. The proposed ECL gate is about 8% faster than the conventional ECL gate. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
00135194
Volume :
39
Issue :
20
Database :
Complementary Index
Journal :
Electronics Letters (Institution of Engineering & Technology)
Publication Type :
Academic Journal
Accession number :
10999866
Full Text :
https://doi.org/10.1049/el:20030940