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A 286 mm/sup 2/ 256 Mb DRAM with /spl times/32 both-ends DQ.

Authors :
Watanabe, Y.
Hing Wong
Kirihata, T.
Kato, D.
DeBrosse, J.K.
Hara, T.
Yoshida, M.
Mukai, H.
Quader, K.N.
Nagai, T.
Poechmueller, P.
Pfefferl, P.
Wordeman, M.R.
Fujii, S.
Source :
IEEE Journal of Solid-State Circuits; 1996, Vol. 31 Issue 4, p567-574, 8p
Publication Year :
1996

Details

Language :
English
ISSN :
00189200
Volume :
31
Issue :
4
Database :
Complementary Index
Journal :
IEEE Journal of Solid-State Circuits
Publication Type :
Academic Journal
Accession number :
92814570
Full Text :
https://doi.org/10.1109/4.499734