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Setting up 3D sequential integration for back-illuminated CMOS image sensors with highly miniaturized pixels with low temperature fully depleted SOI transistors
- Source :
- 2008 IEEE International Electron Devices Meeting.
- Publication Year :
- 2008
- Publisher :
- IEEE, 2008.
-
Abstract
- This paper presents an innovative 3D architecture capable of overcoming pixel miniaturization drawbacks. Back-illuminated photodiodes are realized on a first silicon layer, while readout transistors are located on a second silicon layer. Implications of a sequential integration are evaluated in the perspective of low noise pixel performances with a comprehensive study on: 1/ setting the thermal budget limit to 700degC to preserve transfer gate performances, 2/ transferring high quality SOI by direct bonding 3/ processing HfO2/TiN fully depleted transistors, exhibiting noise levels close to standard 2.2 mum pixels, with improvement solutions.
Details
- Database :
- OpenAIRE
- Journal :
- 2008 IEEE International Electron Devices Meeting
- Accession number :
- edsair.doi...........7197780839b41e2a83bbb291407cbe1b